Jason Li

7881029, Feb 1, 2011

Jul 7, 2008

12/168178

Jason Yuxin Li - Jamestown NC, US
Walter A. Wohlmuth - Greensboro NC, US
Swaminathan Muthukrishnan - Greensboro NC, US
Christian Rye Iversen - Vestbjerg, DK
Nathaniel Peachey - Oak Ridge NC, US

RF Micro Devices, Inc. - Greensboro NC

H02H 3/22

361 56, 361111

The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance and a drain-to-gate resistance of the FET element and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element, a resistive element, a source-coupled level shifting diode, and a reverse protection diode. Therefore, the ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.

7881030, Feb 1, 2011

Jul 7, 2008

12/168179

Jason Yuxin Li - Jamestown NC, US
Walter A. Wohlmuth - Greensboro NC, US
Swaminathan Muthukrishnan - Greensboro NC, US
Christian Rye Iversen - Vestbjerg, DK
Nathaniel Peachey - Oak Ridge NC, US

RF Micro Devices, Inc. - Greensboro NC

H02H 3/22

361 56, 361111

The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance, a drain-to-gate resistance, or both of the FET element, and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element and a resistive element. Therefore, the single FET element ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.

7982243, Jul 19, 2011

May 4, 2007

11/744536

Christian Rye Iversen - Vestbjerg, DK
Jason Yuxin Li - Jamestown NC, US

RF Micro Devices, Inc. - Greensboro NC

H01L 27/10
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119

257202, 257401

The present invention provides a multiple gate transistor architecture that provides an accessible inner source-drain (SD) node. The transistor architecture includes a source structure having multiple source fingers, which extend from a source bus, and a drain structure having multiple drain fingers, which extend from a drain bus. The fingers of the respective source and drain structures are interleaved wherein a meandering path is formed between the source and drain structures. Two or more gate structures run substantially parallel to one another along the meandering path between the source and drain structures. An SD structure is provided between each adjacent pair of gate structures and runs along the meandering path to form the SD node. An SD extension is coupled to the SD structure and accessible by other circuitry to allow a signal to be applied to the SD structure during operation.