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Hui Liu

from Springfield, VA
Age ~58
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Also known as:
Hua Liu, Hanguan Liu, Mui Liu, He Liu, Hui Lui, Elaine A Lew, Liu He, Liu Hanguan, Isodoro Gomez
Phone and address:
7109 Granberry Way, Springfield, VA 22151
(703) 256-6509
Related to:
Jizhong He, 57Weimin Yang, 65Hong Liu, 69Lihua Li, 43Xiannan Li, 41Jun Liu, 57Xiaodong LiuChristopher Yang, 31Mui LiuEric L Yang, 29Yang Hefen, 61Peter Teiyang Ting, 77Jenny He Liu, 56Lexian Liu, 45Bo Yan, 87Jun Liu, 55
Connected to:
Adela Liu, 73Alec X Liu, 39Alpha T Liu, 46Amon Y Liu, 58Andrea Y Liu, 46Anqi Liu, 39Arden K Liu, 64Ba S Liu, 62Bailu Liu, 35Ban Liu, 48

Hui Liu Phones & Addresses

  • 7109 Granberry Way, Springfield, VA 22151 (703) 256-6509
  • Las Vegas, NV
  • San Jose, CA
  • Urbana, MD
  • Ashburn, VA
  • Santa Clara, CA
  • Monmouth Junction, NJ
  • New Brunswick, NJ
  • Gaithersburg, MD

Work

Company: Skirball institute of biomolecular medicine, new york university medical center Aug 2009 Position: Research associate

Education

School / High School: Graduate School of Arts and Science, New York University- New York, NY May 2013 Specialities: Master of Science in Biology

Skills

Immunohistochemistry • Fruit Fly Husbandry • Polyacrylamide Gel Electrophoresis • Polymerase Chain Reaction • Cloning • Fly and Larvae Dissection • Embryo Collection

Specialities

Litigation • Advertising • Intellectual Property • Advertising

Professional Records

Medicine Doctors

Hui Liu Photo 1

Hui Liu

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Specialties:
Nephrology
Work:
Northeast Nephrology
417 State St STE 321, Bangor, ME 04401
(207) 973-8833 (phone), (207) 973-8836 (fax)
Education:
Medical School
Hunan Med Univ, Changsha City, Hunan, China
Graduated: 1997
Conditions:
Acute Renal Failure
Chronic Renal Disease
Languages:
English
Description:
Dr. Liu graduated from the Hunan Med Univ, Changsha City, Hunan, China in 1997. She works in Bangor, ME and specializes in Nephrology. Dr. Liu is affiliated with Eastern Maine Medical Center and St Joseph Hospital.
Hui Liu Photo 2

Hui Liu

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Specialties:
Internal Medicine
Hui Liu Photo 3

Hui Liu

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Specialties:
Pathology
Anatomic Pathology & Clinical Pathology
Education:
Inner Mongolia Medical College (1985)
Hui Liu Photo 4

Hui Xue Liu

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Specialties:
Internal Medicine
Education:
Shanghai Jiao Tong University (1970)

Lawyers & Attorneys

Hui Liu Photo 5

Hui Liu - Lawyer

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Specialties:
Litigation
Advertising
Intellectual Property
Advertising
ISLN:
922902964
Admitted:
2007
University:
Yale Law School

Resumes

Resumes

Hui Liu Photo 6

Hui Hua Liu Brooklyn, NY

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Work:
Skirball Institute of Biomolecular Medicine, New York University Medical Center

Aug 2009 to 2000
Research Associate
University of California at Santa Cruz
Santa Cruz, CA
Apr 2008 to Jun 2009
Undergraduate Researcher
Education:
Graduate School of Arts and Science, New York University
New York, NY
May 2013
Master of Science in Biology
University of California at Santa Cruz
Santa Cruz, CA
Aug 2009
Bachelor of Science in Molecular
Skills:
Immunohistochemistry, Fruit Fly Husbandry, Polyacrylamide Gel Electrophoresis, Polymerase Chain Reaction, Cloning, Fly and Larvae Dissection, Embryo Collection

Business Records

Name / Title
Company / Classification
Phones & Addresses
Hui Min Liu
President
BENEFICIAL SOLUTION, INC
Business Services
2348 Walsh Ave STE C, Santa Clara, CA 95051
261 Chestnut Ave, Palo Alto, CA 94306
Hui Liu
President
SIVAL INSTRUMENTS, INC
Nonclassifiable Establishments
2370 Qume Dr SUITE A2, San Jose, CA 95131
Hui C. Liu
Treasurer
Achates International Inc
Wholesales Crude Oil & Commodities and Exports Defense & Commercial Equip & Imports Computer Hardware & Video Games
15200 Shady Grv Rd, Rockville, MD 20850
(301) 670-2836
Hui Liu
Max Material, LLC
Investment Business · Retail Materials
998 Westlynn Way, Cupertino, CA 95014
512 Troy Dr, San Jose, CA 95117
Hui Liu
Running River Investment LLC
1643 Thorncrest Dr, San Jose, CA 95131
Hui Liu
CHEN LIU LLC
Hui Zhu Liu
ZHENG & LIU, INC
Hui Liu
President
STERLING BRIDGE CAPITAL, INC
Mfg Communications Equipment · Investment Advisory Service
637 Howard St, San Francisco, CA 94105
848 Stewart Dr, Sunnyvale, CA 94085

Publications

Us Patents

Method And System For Improving Memory Interface Data Integrity In Plds

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US Patent:
7102544, Sep 5, 2006
Filed:
May 31, 2005
Appl. No.:
11/142732
Inventors:
Hui Liu - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03M 7/34
US Classification:
341 51, 341 50, 711119
Abstract:
An integrated circuit (IC) for optimizing data presentation to an external memory interface bus is provided. The IC is in communication with the external memory via the external memory interface bus. The IC includes an encoder that may encode the data that are being sent to an external memory. The encoder encodes the data based on the logic value of the majority of bits in the data. The encoder is capable of setting a status bit to indicate that the data are encoded. Further connected in series with the encoder is a parity generator that sets the parity bit logic value based on whether the number of logic s in the data, along with the status bit, is even or odd. The IC also includes a parity checker to detect whether any error occurred in the data during transmission. The decoder within the IC decodes the data to the original data.

Method And System For Improving Memory Interface Data Integrity

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US Patent:
7352299, Apr 1, 2008
Filed:
Nov 16, 2006
Appl. No.:
11/560673
Inventors:
Hui Liu - Pleasanton CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03M 7/00
US Classification:
341 51, 341 50
Abstract:
An integrated circuit (IC) for optimizing data presentation to an external memory interface bus is provided. The IC is in communication with the external memory via the external memory interface bus. The IC includes an encoder that may encode the data that are being sent to an external memory. The encoder encodes the data based on the logic value of the majority of bits in the data. The encoder sets a status bit to indicate that the data are encoded. The encoder includes two encoding stages to further enhance the data integrity and transfer. Further connected in series with the encoder is a parity generator that sets the parity bit logic value based on whether the number of logic 1s in the data, including the status bit, is even or odd. The IC also includes a parity checker to detect whether any error occurred in the data during transmission. The decoder within the IC decodes the data to the original data.

Programmable Logic Device With Power Supply Noise Monitoring

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US Patent:
7359811, Apr 15, 2008
Filed:
Jun 16, 2005
Appl. No.:
11/153984
Inventors:
Hui Liu - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G05F 1/40
US Classification:
702 69, 326 38
Abstract:
Programmable logic device power supply noise levels are characterized using internal measurements. By making power supply noise measurements internally, noise measurements are made without influence from device packaging or circuit board environmental effects. The input-output circuitry of a programmable logic device is configured to supply a power supply voltage from the output of an output buffer to one of the inputs of a differential input buffer. The other of the inputs of the differential input buffer is provided with a reference voltage from an external voltage reference circuit. The differential input buffer serves as a comparator and generates an output signal based on a comparison of the power supply voltage from the output buffer and the reference voltage. A noise monitoring circuit processes the output of the input buffer. The noise monitoring circuit may be based on a register.

System For Improving Memory Interface Data Integrity In Plds

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US Patent:
7400273, Jul 15, 2008
Filed:
Jul 20, 2006
Appl. No.:
11/458962
Inventors:
Hui Liu - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03M 7/00
US Classification:
341 51, 341 50
Abstract:
An integrated circuit (IC) for optimizing data presentation to an external memory interface bus is provided. The IC is in communication with the external memory via the external memory interface bus. The IC includes an encoder that may encode the data that are being sent to an external memory. The encoder encodes the data based on the logic value of the majority of bits in the data. The encoder is capable of setting a status bit to indicate that the data are encoded. Further connected in series with the encoder is a parity generator that sets the parity bit logic value based on whether the number of logic 1s in the data, along with the status bit, is even or odd. The IC also includes a parity checker to detect whether any error occurred in the data during transmission. The decoder within the IC decodes the data to the original data.

Differential Vertical Structure For High Density, Low Layer Count Packages

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US Patent:
8119931, Feb 21, 2012
Filed:
Feb 27, 2009
Appl. No.:
12/395424
Inventors:
Hui Liu - Pleasanton CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H05K 1/11
US Classification:
174262
Abstract:
A multilayer substrate minimizing differential loss is presented. The multilayer substrate for providing signals between an integrated circuit and a printed circuit board consists of a number of alternating electrically conductive and insulating layers. Differential signals are routed through the core insulating layer using differential pairs of plated through holes (PTHs). In addition, the multilayer substrate includes a number of plated through holes, which provide ground signals between conductive layers separated by the core layer. The multilayer substrate is configured such that a PTH providing ground is situated between each differential pair of plated ground holes, where the center or axis of each plated through hole is aligned in a collinear configuration.

Interconnect Pattern For High Performance Interfaces

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US Patent:
8232480, Jul 31, 2012
Filed:
Feb 9, 2010
Appl. No.:
12/702823
Inventors:
Hui Liu - Pleasanton CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H05K 1/11
US Classification:
174261, 361772, 361777
Abstract:
In one embodiment, differential signaling and ground contacts are located in a rectilinear array of rows and columns with ground contacts spaced apart by three times the pitch distance between adjacent rows or columns and signaling contacts are located immediately adjacent the ground contacts. In particular, the two contacts of each differential pair are located one pitch distance apart from each other and one contact of each differential pair of contacts is located one pitch distance from a ground contact and the other contact of the differential pair is located approximately sqrt(2)*pitch distance from the same ground contact. In a second embodiment, differential signaling and ground contacts are located in a hexagonal array with ground contacts located three times the pitch distance between adjacent contacts and signaling contacts located immediately adjacent the ground contacts. In particular, the two contacts of each differential pair are located one pitch distance apart from each other and both contacts of each differential pair of contacts are located one pitch distance from a ground contact.

Power Distribution Network

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US Patent:
8498129, Jul 30, 2013
Filed:
Jun 10, 2011
Appl. No.:
13/158034
Inventors:
Hui Liu - Pleasanton CA, US
Hong Shi - Fremont CA, US
Yuanlin Xie - Fremont CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H05K 1/18
H05K 7/00
H05K 1/14
US Classification:
361764, 361760, 361763, 361737
Abstract:
An improved power distribution network for an integrated circuit package that reduces the number of power supply pins that are used in the pin array and achieves better operating performance. In a preferred embodiment, the ratio of power supply pins to input/output (I/O) pins is in the range of approximately 1 to 24 to approximately 1 to 52. In this embodiment, the integrated circuit package comprises a substrate, an integrated circuit mounted on the substrate, a first decoupling capacitor mounted on the substrate, and a second decoupling capacitor formed in the integrated circuit. The package is formed by coupling a power supply pin to both the first and second capacitors by a low frequency path and a DC path, respectively, and the first and second capacitors are coupled by a high frequency path.

Precursor Detection Using Correlation In Time-Domain In An Ofdm Communications System

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US Patent:
20080025420, Jan 31, 2008
Filed:
Oct 17, 2006
Appl. No.:
11/550403
Inventors:
HUI LIU - Fremont CA, US
Dinesh Venkatachalam - Fremont CA, US
Assignee:
LEGEND SILICON - Fremont CA
International Classification:
H04K 1/10
US Classification:
375260
Abstract:
In an OFDM (Orthogonal frequency-division multiplexing) communication system having a PN sequence as guard area, a code acquisition method is provided. The method includes the steps of: determining a precursor to a main peak using correlation; and using the precursor as a starting point for a new frame.

Isbn (Books And Publications)

The Nine Chapters on the Mathematical Art: Companion and Commentary

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Author

Hui Liu

ISBN #

0198539363

OFDM-Based Broadband Wireless Networks: Design And Optimization

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Author

Hui Liu

ISBN #

0471723460

OFDM-Based Broadband Wireless Networks: Design and Optimization

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Author

Hui Liu

ISBN #

0471757187

Ofdm-based Broadband Wireless Networks: Design and Optimization

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Author

Hui Liu

ISBN #

0471757195

Iap Global Ocean-Atmosphere-Land System Model

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Author

Hui Liu

ISBN #

7030078608

Amazon

Fluid Flow in the Subsurface: History, Generalization and Applications of Physical Laws (Theory and Applications of Transport in Porous Media)

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This book presents a systematic attempt to generalize several fundamental physical laws related to subsurface fluid flow that are important for a number of contemporary applications in the areas of hydrogeology, reservoir engineering and rock mechanics. It also covers the history of discovering thes...
Author

Hui Hai Liu

Binding

Kindle Edition

Pages

230

Publisher

Springer

ISBN #

16

Business Chinese 500

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Business Chinese 500 is designed for the increasing number of business people who are going to China to conduct business who have progressed beyond the elementary level in Chinese. This book is composed of 22 lessons, each lesson consists of useful sentences, substitution drills, short dialogs, new ...
Author

Liu Yan Hui, Liu Ye Qing

Binding

Paperback

Pages

200

Publisher

Sinolingua

ISBN #

7802004012

ISBN #

10

OFDM-Based Broadband Wireless Networks: Design and Optimization

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OFDM-based Broadband Wireless Networks covers the latest technological advances in digital broadcasting, wireless LAN, and mobile networks to achieve high spectral efficiency, and to meet peak requirements for multimedia traffic. The book emphasizes the OFDM modem, air-interface, medium access-contr...
Author

Hui Liu, Guoqing Li

Binding

Hardcover

Pages

251

Publisher

Wiley-Interscience

ISBN #

0471723460

EAN Code

9780471723462

ISBN #

9

The Kanshi Poems of Taigu Ryokan (Laughing Buddha Series) (English, Chinese and Japanese Edition)

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100 poems by Japanese poet Taigu Ryokan (1758-1831) included in English, original Chinese, and Japanese by poets Mei Hui Liu Huang and Larry Smith. With an introduction "Taigu Ryokan: Great Fool" by Larry Smith. Contains Poems of Children 童 心; My Hut 草 庵; Travel Poems 行 腳 ; Poems of Friendship 友 情 ;...
Author

Taigu Ryokan

Binding

Paperback

Pages

168

Publisher

Bottom Dog Press

ISBN #

1933964251

EAN Code

9781933964256

ISBN #

5

Packaging of High Power Semiconductor Lasers (Micro- and Opto-Electronic Materials, Structures, and Systems)

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This book introduces high power semiconductor laser packaging design.The challenges of the design and various packaging and testing techniques are detailed by the authors. New technologies and current applications are described in detail.
Author

Xingsheng Liu, Wei Zhao, Lingling Xiong, Hui Liu

Binding

Hardcover

Pages

402

Publisher

Springer

ISBN #

1461492629

EAN Code

9781461492627

ISBN #

3

meditation(Chinese Edition)

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Author

(GU LUO MA)AO LE LIU CHEN HUI ZHEN DENG LIU YAN YI

Binding

Paperback

Publisher

Jilin University Press Pub. Date :2008-09-01

ISBN #

7560139051

EAN Code

9787560139050

ISBN #

14

Liu Hui Annotation

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Author

GUO SHU CHUN YI ZHU

Binding

Hardcover

Publisher

Unknown

ISBN #

7532554333

EAN Code

9787532554331

ISBN #

4

LIU ZU TAN JING: 六祖坛经

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Author

LIU ZU HUI NENG

Binding

Kindle Edition

Pages

40

ISBN #

1

Control profile
Hui Liu from Springfield, VA, age ~58 Get Report