Hui Z Nie

8558242, Oct 15, 2013

Dec 9, 2011

13/315705

Richard J. Brown - Los Gatos CA, US
Hui Nie - Cupertino CA, US
Andrew Edwards - San Jose CA, US
Isik Kizilyalli - San Francisco CA, US
David Bour - Cupertino CA, US
Thomas Prunty - Santa Clara CA, US
Linda Romano - Sunnyvale CA, US
Madhan Raj - Cupertino CA, US

Avogy, Inc. - San Jose CA

H01L 29/20

257 76, 257200, 257201, 257E29089, 257E2109

A semiconductor structure includes a III-nitride substrate having a top surface and an opposing bottom surface and a first III-nitride layer of a first conductivity type coupled to the top surface of the III-nitride substrate. The semiconductor structure also includes a second III-nitride layer of a second conductivity type coupled to the first III-nitride layer along a vertical direction and a third III-nitride layer of a third conductivity type coupled to the second III-nitride layer along the vertical direction. The semiconductor structure further includes a first trench extending through a portion of the third III-nitride layer to the first III-nitride layer, a second trench extending through another portion of the third III-nitride layer to the second III-nitride layer, and a first metal layer coupled to the second and the third III-nitride layers.

8569153, Oct 29, 2013

Nov 30, 2011

13/307108

David P. Bour - Cupertino CA, US
Thomas R. Prunty - Santa Clara CA, US
Linda Romano - Sunnyvale CA, US
Richard J. Brown - Los Gatos CA, US
Isik C. Kizilyalli - San Francisco CA, US
Hui Nie - Cupertino CA, US

Avogy, Inc. - San Jose CA

H01L 21/20
H01L 21/337

438488, 438192, 438503

A method of growing an n-type III-nitride-based epitaxial layer includes providing a substrate in an epitaxial growth reactor, forming a masking material coupled to a portion of a surface of the substrate, and flowing a first gas into the epitaxial growth reactor. The first gas includes a group III element and carbon. The method further comprises flowing a second gas into the epitaxial growth reactor. The second gas includes a group V element, and a molar ratio of the group V element to the group III element is at least 5,000. The method also includes growing the n-type III-nitride-based epitaxial layer.

8592298, Nov 26, 2013

Dec 22, 2011

13/335355

Linda Romano - Sunnyvale CA, US
David P. Bour - Cupertino CA, US
Andrew Edwards - San Jose CA, US
Hui Nie - Cupertino CA, US
Isik C. Kizilyalli - San Francisco CA, US
Richard J. Brown - Los Gatos CA, US
Thomas R. Prunty - San Clara CA, US

Avogy, Inc. - San Jose CA

H01L 21/3205

438604, 257E21085, 257E21097, 257E21108, 257E21172, 257E21403, 257458, 257483, 257484, 257489, 257615, 438167, 438186, 438570

A method for fabricating edge termination structures in gallium nitride (GaN) materials includes providing a n-type GaN substrate having a first surface and a second surface, forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate, and forming a growth mask coupled to the n-type GaN epitaxial layer. The method further includes patterning the growth mask to expose at least a portion of the n-type GaN epitaxial layer, and forming at least one p-type GaN epitaxial structure coupled to the at least a portion of the n-type GaN epitaxial layer. The at least one p-type GaN epitaxial structure comprises at least one portion of an edge termination structure. The method additionally includes forming a first metal structure electrically coupled to the second surface of the n-type GaN substrate.

8592938, Nov 26, 2013

Nov 18, 2011

13/300028

Madhan Raj - Cupertino CA, US
Richard J. Brown - Los Gatos CA, US
Thomas R. Prunty - Santa Clara CA, US
David P. Bour - Cupertino CA, US
Isik C. Kizilyalli - San Francisco CA, US
Hui Nie - Cupertino CA, US
Andrew P. Edwards - San Jose CA, US
Linda Romano - Sunnyvale CA, US

Avogy, Inc. - San Jose CA

H01L 29/47

257472, 257 73, 257267, 257280, 257473

A method for fabricating a III-nitride semiconductor device includes providing a III-nitride substrate having a first surface and a second surface opposing the first surface, forming a III-nitride epitaxial layer coupled to the first surface of the III-nitride substrate, and removing at least a portion of the III-nitride epitaxial layer to form a first exposed surface. The method further includes forming a dielectric layer coupled to the first exposed surface, removing at least a portion of the dielectric layer, and forming a metallic layer coupled to a remaining portion of the dielectric layer such that the remaining portion of the dielectric layer is disposed between the III-nitride epitaxial layer and the metallic layer.

8643134, Feb 4, 2014

Nov 18, 2011

13/300028

Madhan Raj - Cupertino CA, US
Richard J. Brown - Los Gatos CA, US
Thomas R. Prunty - Santa Clara CA, US
David P. Bour - Cupertino CA, US
Isik C. Kizilyalli - San Francisco CA, US
Hui Nie - Cupertino CA, US
Andrew P. Edwards - San Jose CA, US
Linda Romano - Sunnyvale CA, US

Avogy, Inc. - San Jose CA

H01L 29/47

257472, 257 73, 257267, 257280, 257473

A method for fabricating a III-nitride semiconductor device includes providing a III-nitride substrate having a first surface and a second surface opposing the first surface, forming a III-nitride epitaxial layer coupled to the first surface of the III-nitride substrate, and removing at least a portion of the III-nitride epitaxial layer to form a first exposed surface. The method further includes forming a dielectric layer coupled to the first exposed surface, removing at least a portion of the dielectric layer, and forming a metallic layer coupled to a remaining portion of the dielectric layer such that the remaining portion of the dielectric layer is disposed between the III-nitride epitaxial layer and the metallic layer.

20110083722, Apr 14, 2011

Oct 13, 2010

12/904047

Harry ATWATER - South Pasadena CA, US
Brendan KAYES - Santa Clara CA, US
Isik C. KIZILYALLI - San Francisco CA, US
Hui NIE - Santa Clara CA, US

ALTA DEVICES, INC. - Santa Clara CA

H01L 31/0236
H01L 31/0232
H01L 31/18

136246, 438 71, 257E31127, 257E3113

Embodiments of the invention generally relate to device fabrication of thin films used as solar devices or other electronic devices, and include textured back reflectors utilized in solar applications. In one embodiment, a method for forming a textured metallic back reflector which includes depositing a metallic layer on a gallium arsenide material within a thin film stack, forming an array of metallic islands from the metallic layer during an annealing process, removing or etching material from the gallium arsenide material to form apertures between the metallic islands, and depositing a metallic reflector layer to fill the apertures and cover the metallic islands. In another embodiment, a textured metallic back reflector includes an array of metallic islands disposed on a gallium arsenide material, a plurality of apertures disposed between the metallic islands and extending into the gallium arsenide material, a metallic reflector layer disposed over the metallic islands, and a plurality of reflector protrusions formed between the metallic islands and extending from the metallic reflector layer and into the apertures formed in the gallium arsenide material.

20120104460, May 3, 2012

Nov 3, 2010

12/939077

Hui NIE - Santa Clara CA, US
Brendan M. KAYES - San Francisco CA, US
Isik C. KIZILYALLI - San Francisco CA, US

ALTA DEVICES, INC. - Santa Clara CA

H01L 31/109
H01L 21/04

257184, 438 94, 257E31067, 257E2104

Embodiments of the invention generally relate to optoelectronic semiconductor devices such as photovoltaic devices including solar cells. In one aspect, an optoelectronic semiconductor device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device, the emitter layer made of a different material than the absorber layer and having a higher bandgap than the absorber layer. A heterojunction formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. The p-n junction causes a voltage to be generated in the device in response to the device being exposed to light at a front side of the device.

20120199184, Aug 9, 2012

Feb 9, 2011

13/023733

Hui NIE - Cupertino CA, US
Brendan M. Kayes - San Francisco CA, US
Isik C. Kizilyalli - San Francisco CA, US

Alta Devices, Inc. - Santa Clara CA

H01L 31/06
H01L 31/0352

136255, 438 94, 257E31032

Embodiments of the invention generally relate to photovoltaic devices. In one embodiment, a method for forming a gallium arsenide based photovoltaic device includes providing a semiconductor structure, the structure including an absorber layer comprising gallium arsenide. A bypass function is provided in a p-n junction of the semiconductor structure, where under reverse-bias conditions the p-n junction breaks down in a controlled manner by a Zener breakdown effect.