Search

Yu N Cai

from La Puente, CA
Age ~47
Get Report
Also known as:
Yu H Cai, Ning Cai Yu
Related to:
Yumei ShiYu Ruan, 89Liv Yuwei
Connected to:
Anping Cai, 46Bao K Cai, 67Beibei Cai, 35Biaodong Cai, 62Caitlin Cai, 34Cecilia Y Cai, 35Changqing Cai, 58Chao Cai, 45Chunli Cai, 52Cristina Cai, 41

Yu Cai Phones & Addresses

  • La Puente, CA
  • Redmond, WA
  • 1805 S Primrose Ave, Alhambra, CA 91803 (626) 457-8083
  • 916 Atlantic Blvd, Alhambra, CA 91803 (626) 576-0489
  • 916 S Atlantic Blvd APT 6, Alhambra, CA 91803 (818) 590-3902
  • San Jose, CA
  • Milpitas, CA
  • San Gabriel, CA
  • Monterey Park, CA
  • La Puente, CA

Resumes

Resumes

Yu Cai Photo 1

Office Clerk

View page
Location:
Rowland Heights, CA
Industry:
Consumer Services
Work:
Solid Wing Trading
Office Clerk
Yu Cai Photo 2

Yu Cai

View page
Location:
Seattle, WA
Industry:
Insurance
Work:
Crawford & Company
Lead Software Engineer and Release Manager
Broadspire Jul 2002 - Jun 2011
Senior Software Engineer
Pyhcom Corporation Nov 1999 - Feb 2002
Senior Server Engineer
Volt Computer Services Jan 1999 - Oct 1999
Sdet
Greater Seattle Area Jan 1999 - Oct 1999
Education:
The University of Southern Mississippi 1996 - 1998
Masters, Computer Science University of Sothern Mississippi
Tongji University
Bachelors, Bachelor of Science
Skills:
T Sql
Microsoft Sql Server
.Net
Software Development Life Cycle
Web Services
C++
Oracle Certified Dba
Java
C#
Oo Software Development
Requirements Analysis
Software Development
Asp.net Mvc
Asp.net
Databases
Pl/Sql
Agile Methodologies
Unix
Web Applications
Integration
Data Warehousing
Sql
Software Project Management
Xml
Object Oriented Design
Certifications:
Oracle 8 - 11G Certified Dba
Yu Cai Photo 3

Yu Cai

View page
Yu Cai Photo 4

Yu Cai

View page
Yu Cai Photo 5

Yu Cai

View page
Yu Cai Photo 6

Senior System Engineer At Huawei

View page
Position:
Senior Design Engineer/State Key Laboratory of Radio Access Technologies at Huawei
Location:
Shenzhen, Guangdong, China
Industry:
Wireless
Work:
Huawei - China since Mar 2012
Senior Design Engineer/State Key Laboratory of Radio Access Technologies
Bitswave Inc Jan 2011 - Mar 2012
DSP Hardware Engineer
Texas Instruments Aug 2010 - Dec 2010
Application Engineer
Halliburton Sep 2009 - Aug 2010
Senior Design Engineer
Subsurface sensing laboratory, University of Houston Jan 2006 - Jul 2009
Research Assistant/DSP Engineer
Education:
University of Houston 2006 - 2009
PhD, Electrical Engineering University of Cincinnati 2003 - 2006
Xi'an Jiaotong University 1999 - 2002
Master of Science; Bachelor of Science, Electrical Engineering Xi'an Jiaotong University 1995 - 1999
BS, EE
Yu Cai Photo 7

Yu Cai

View page
Location:
United States
Yu Cai Photo 8

Yu Cai

View page
Location:
United States

Business Records

Name / Title
Company / Classification
Phones & Addresses
Yu Cai
Manager
Tawa Supermarket, Inc
Ret Groceries
1300 S Golden West Ave, Arcadia, CA 91007
(626) 445-7899
Yu Feng Cai
CONNECT INT'L NETWORK INC

Publications

Us Patents

Soft Chip-Kill Recovery For Multiple Wordlines Failure

View page
US Patent:
20200319970, Oct 8, 2020
Filed:
Jun 18, 2020
Appl. No.:
16/905787
Inventors:
- Gyeonggi-do, KR
Aman Bhatia - San Jose CA, US
Chenrong Xiong - San Jose CA, US
Yu Cai - San Jose CA, US
Fan Zhang - Fremont CA, US
International Classification:
G06F 11/10
G11C 29/52
H03M 13/37
H03M 13/45
H03M 13/11
H03M 13/13
H03M 13/29
Abstract:
Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when reading data from a superblock of the memory, where the decoding of multiple wordlines failed, a computer system schedules the decoding of failed wordlines based on quantity of bit errors and updates soft information based on convergence or divergence of the scheduled decoding. Such a computer system significantly reduces decoding failures associated with data reads from the memory and allows improved data retention in the memory.

Soft Chipkill Recovery For Bitline Failures

View page
US Patent:
20200210286, Jul 2, 2020
Filed:
Dec 17, 2019
Appl. No.:
16/717857
Inventors:
- Icheon-si, KR
Chenrong Xiong - San Jose CA, US
Aman Bhatia - San Jose CA, US
Yu Cai - San Jose CA, US
Fan Zhang - San Jose CA, US
International Classification:
G06F 11/10
H03M 13/11
H03M 13/45
Abstract:
Disclosed are devices, systems and methods for improving performance of a block of a memory device. In an example, performance is improved by implementing soft chipkill recovery to mitigate bitline failures in data storage devices. An exemplary method includes encoding each horizontal row of cells of a plurality of memory cells of a memory block to generate each of a plurality of codewords, and generating a plurality of parity symbols, each of the plurality of parity symbols based on diagonally positioned symbols spanning the plurality of codewords.

Storage Device Performance Optimization Using Deep Learning

View page
US Patent:
20200210831, Jul 2, 2020
Filed:
Dec 17, 2019
Appl. No.:
16/717888
Inventors:
- Icheon-si, KR
Yu Cai - San Jose CA, US
Chenrong Xiong - San Jose CA, US
Xuanxuan Lu - San Jose CA, US
International Classification:
G06N 3/08
G06N 3/04
Abstract:
Disclosed is a computer-implemented method for optimizing read thresholds of a memory device using a deep neural network engine, comprising reading, using a set of read threshold voltages applied to the memory device, data from the memory device under a first set of operating conditions that contribute to read errors in the memory device, producing a labeled training data set using the set of read threshold voltages under the first set of the operating conditions, determining, based on characteristics of the memory device, a number of layers, a size of each layer, and a number of input and output nodes of the deep neural network engine, training the deep neural network engine using the labeled training data set, and using the trained deep neural network engine to compute read thresholds voltage values under a second set of operating conditions.

Memory System And Method For Read Operation Based On Grouping Of Word Lines

View page
US Patent:
20200185040, Jun 11, 2020
Filed:
Dec 11, 2019
Appl. No.:
16/711003
Inventors:
- Gyeonggi-do, KR
Chenrong XIONG - San Jose CA, US
Fan ZHANG - Fremont CA, US
Naveen KUMAR - San Jose CA, US
Xuanxuan LU - San Jose CA, US
Yu CAI - San Jose CA, US
International Classification:
G11C 16/26
G11C 16/04
G11C 16/30
G11C 16/08
G06F 12/10
Abstract:
A memory system includes a memory device and a controller. The controller determines a target word line group to which a target word line corresponding to a read command belongs. The controller identifies a reference voltage corresponding to the target word line group. The controller controls the memory device to perform a read operation on a target page coupled to the target word line, using the reference voltage.

Memory System To Process Multiple Word Line Failures With Limited Storage And Method Of Operating Such Memory System

View page
US Patent:
20200090731, Mar 19, 2020
Filed:
Sep 18, 2019
Appl. No.:
16/575224
Inventors:
- San Jose CA, US
Yu CAI - San Jose CA, US
Fan ZHANG - San Jose CA, US
International Classification:
G11C 11/408
G11C 11/409
G11C 29/12
H03M 13/45
H03M 13/25
Abstract:
Systems, memory controllers, decoders and methods perform decoding by exploiting differences among word lines for which soft decoding fails (failed word lines). Such decoding generates extrinsic information for codewords of failed word lines based on the soft decoding. The soft information obtained during the soft decoding is updated based on the extrinsic information, and the updated soft information is propagated across failed word lines. Low-density parity-check (LDDC) decoding of codewords of failed word lines is performed with the updated soft information.

Dynamic Neighbor And Bitline Assisted Correction For Nand Flash Storage

View page
US Patent:
20200042384, Feb 6, 2020
Filed:
May 23, 2019
Appl. No.:
16/421204
Inventors:
- Gyeonggi-do, KR
Aman Bhatia - San Jose CA, US
Yu Cai - San Jose CA, US
Fan Zhang - San Jose CA, US
International Classification:
G06F 11/10
G11C 29/52
H03M 13/45
Abstract:
A storage system includes memory cells arranged in an array and a memory controller coupled to the memory cells for controlling operations of the memory cells. The memory controller is configured to perform a read operation in response to a read command from a host, perform a first soft decoding of data from the read operation using existing LLR (log likelihood ratio) values stored in the memory controller, update existing LLR values using LLR values from neighboring memory cells and existing weight coefficients that account for influence from the neighboring memory cells. The memory controller is also configured to perform a second soft decoding using the updated LLR values. If the second soft decoding is successful, the memory controller performs a recursive update of weight coefficients to reflect updated influence from neighboring memory cells and stores the updated weight coefficient in the memory controller for use in further decoding.

Memory System And Method For Optimizing Read Threshold

View page
US Patent:
20200027519, Jan 23, 2020
Filed:
Jul 23, 2019
Appl. No.:
16/519445
Inventors:
- San Jose CA, US
Yu CAI - San Jose CA, US
Chenrong XIONG - San Jose CA, US
Xuanxuan LU - San Jose CA, US
International Classification:
G11C 29/38
G06F 3/06
Abstract:
A memory system includes a memory device and a controller. The controller performs a test read operation on a read data set of the memory device, using multiple read threshold entries and determines which are good read threshold entries based on results of the read operation. The controller selects a best read threshold entry among the multiple read threshold entries based on a result of the test read operation, partitions the read data set into a good data set decodable by the best read threshold entry and a bad data set undecodable by the best read threshold entry, and sets the bad data set as a new read data set.

Media Quality Aware Ecc Decoding Method Selection To Reduce Data Access Latency

View page
US Patent:
20200004626, Jan 2, 2020
Filed:
Sep 9, 2019
Appl. No.:
16/565120
Inventors:
- Gyeonggi-do, KR
Fan ZHANG - Fremont CA, US
Yu CAI - San Jose CA, US
International Classification:
G06F 11/10
Abstract:
A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action.
Control profile
Yu N Cai from La Puente, CA, age ~47 Get Report