Chinh Hoang Vo

8116145, Feb 14, 2012

Aug 29, 2008

12/202048

Pearl P. Cheng - Los Altos CA, US
Harry S. Luan - Saratoga CA, US
Chinh Vo - San Jose CA, US
Chih-Chieh (Steve) Wang - Fremont CA, US

Kilopass Technology, Inc. - Santa Clara CA

G11C 7/00

36518907, 36518518

A method and system for enabling auto shut-off of programming of a non-volatile memory cell is disclosed. The system includes a memory array having a plurality of memory cells, each cell storing one bit of data. During the programming process, programming signals are applied to the target memory cells. A predefined period of time after the programming signals are applied, the auto shut-off system begins sensing an output signal from the memory cell. After the system detects an output signal from the memory cell, the system waits for a second predefined period of time before turning off the programming voltages. The system may be configured to sense an output voltage from the memory cell. The system then compares the output voltage to a reference voltage in order to detect when the cell is programmed. Alternatively, the system may sense an output current from the memory cell. The system then compares the output current to a reference current to detect when the cell is programmed.

20090080275, Mar 26, 2009

Sep 20, 2007

11/858515

Chinh Vo - San Jose CA, US
Harry Shengwen Luan - Saratoga CA, US
Pearl Cheng - Los Altos CA, US

G11C 7/02

365206

In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations.

20210397372, Dec 23, 2021

Jun 22, 2020

16/907411

- Addison TX, US
Nihal Singla - Bangalore, IN
Chinh Vo - San Jose CA, US

SanDisk Technologies LLC - Addison TX

G06F 3/06
H01L 25/18
H01L 23/00
G11C 16/04
G11C 16/10

An apparatus is provided that includes a memory die including a pipeline circuit coupled to a memory structure. The memory die is configured to execute a first command by receiving in the pipeline circuit data to be written to the memory structure, processing the received data in the pipeline circuit and providing the processed data to the memory structure, predicting that the pipeline circuit has completed processing the received data, and ending execution of the first command based on the prediction.

20180095489, Apr 5, 2018

Sep 30, 2016

15/283232

- San Jose CA, US
Chinh Vo - San Jose CA, US

G05F 1/575

An output circuit at the output of an LDO regulator has two FETs (Field-Effect Transistors), a current source and a capacitor. The first FET is connected to the LDO output and a second voltage supply. The second FET is connected in series with the current source between the LDO output and the second voltage supply. The second FET is connected to the first FET in such a matter that a bias voltage is supplied to the first FET so that in static conditions the first FET draws predetermined amounts of current from the LDO output and to divert the predetermined amounts of current to the LDO output or to draw additional amounts of current from the LDO output to compensate for transient currents on the LDO output and to reduce variations in the output voltage of the LDO regulator. The capacitor with the current source defines a time constant to control the recovery of the output circuit from sudden drops or rises in voltage at the LDO regulator output to allow the LDO regulator to respond without adverse effect to the LDO output voltage.

20180096730, Apr 5, 2018

Sep 30, 2016

15/283195

- San Jose CA, US
Chinh Vo - San Jose CA, US

G11C 17/18
G11C 17/16

A differential current sensing circuit architecture is used with an integrated circuit NVM memory block in which a selected memory cell and a related complementary memory cell are accessed at the same time for reading. The circuit architecture is used not only for normal operations for reading the logic states of a selected memory cell and its complementary memory cell after programming, but also for reading the logic states of a selected memory cell and its complementary memory cell before programming for the detecting of faults in memory cells.