Chi Tan Chan

7673201, Mar 2, 2010

Mar 12, 2009

12/402728

Chi Bun Chan - San Jose CA, US
Jingzhao Ou - Sunnyvale CA, US

XILINX, Inc. - San Jose CA

G01R 31/28
G06F 7/38
H03K 19/00

714725, 714731, 326 40, 716 17

A method of restoring a selected operational state of a circuit design implemented within a programmable integrated circuit (IC) can include pipelining a clock gating signal that selectively pauses a clock of the circuit design, and storing configuration data specifying an operational state of the circuit design at a first simulation clock cycle in non-configuration memory. At a second simulation clock cycle, the clock of the circuit design can be gated. The stored configuration data can be loaded into configuration memory of the programmable IC, wherein loading the configuration data reconfigures the circuit design and restores the operational state of the circuit design in existence at the first simulation clock cycle. The clock of the circuit design can be advanced a number of clock cycles corresponding to a difference between the second simulation clock cycle and the first simulation clock cycle.

7746099, Jun 29, 2010

Jan 11, 2008

12/008489

Chi Bun Chan - San Jose CA, US
Nabeel Shirazi - San Jose CA, US

Xilinx, Inc. - San Jose CA

H03K 19/173

326 38, 326 8

A method of implementing a circuit in a device having programmable logic is disclosed. The method comprises implementing a circuit in the programmable logic of the device; storing data in a block of random access memory; performing a partial reconfiguration of the device, where new data is stored in the block of random access memory; and accessing the new data. A system of implementing a circuit in a device having programmable logic is also disclosed.

7747423, Jun 29, 2010

Sep 27, 2006

11/527841

Nabeel Shirazi - San Jose CA, US
Jonathan B. Ballagh - Boulder CO, US
Chi Bun Chan - Longmont CO, US

Xilinx, Inc. - San Jose CA

G06F 17/50

703 13, 703 14

Systems and methods of performing co-simulation of a partitioned circuit design using multiple programmable logic devices (PLDs) coupled together to form a boundary scan chain. A host computer is coupled to the scan chain via a programming cable. Resident on the host computer are run-time co-simulation blocks corresponding to blocks from the circuit design, where each block is designated to run on one of the PLDs in the scan chain; a programming cable device driver interfacing with the programming cable; and a proxy component. The proxy component is coupled to all of the run-time co-simulation blocks and the programming cable device driver. Each co-simulation block includes a unique pattern identifier, which is also present in the associated PLD. Using this pattern identifier, data and commands targeted to a specific PLD can be extracted from the scan chain, while ignoring data and commands targeted to other PLDs in the scan chain.

7852109, Dec 14, 2010

Dec 15, 2008

12/335466

Chi Bun Chan - San Jose CA, US
Jingzhao Ou - Sunnyvale CA, US

Xilinx, Inc. - San Jose CA

H03K 19/00

326 16, 326 47, 326 93

A method and apparatus involves operating a circuit having a test circuit interrupt input terminal (INTERRUPT), having a test circuit clock output terminal (DUT_CLK), and having first and second operational modes. In the first operational mode the circuit supplies a test circuit clock signal to the test circuit clock output terminal. The circuit responds to receipt of an occurrence of a test circuit interrupt at the test circuit interrupt input terminal by then operating in the second operational mode. In the second operational mode the circuit refrains from supplying the test circuit clock signal to the test circuit clock output terminal.

7930162, Apr 19, 2011

May 5, 2008

12/115340

Chi Bun Chan - San Jose CA, US
Shay Ping Seng - San Jose CA, US
Jingzhao Ou - Sunnyvale CA, US

Xilinx, Inc. - San Jose CA

G06F 17/50

703 14, 714724

An integrated circuit configured for hardware co-simulation can include a command processor, a replay buffer storing a command template, wherein the command template specifies an incomplete command, and a command first-in-first out (FIFO) memory storing complementary data for completion of the command template. The integrated circuit further can include a multiplexer coupled to the command processor, the replay buffer, and the command FIFO. The multiplexer, under control of the command processor, can selectively provide data from the replay buffer or the command FIFO to the command processor. The command processor, responsive to a replay command read during a hardware co-simulation session, can enter a replay mode, obtain the command template from the replay buffer, obtain the complementary data from the FIFO memory according to a symbol read from the command template, and form a complete command by joining the command template with the complementary data.

7937259, May 3, 2011

Dec 18, 2007

12/002838

Chi Bun Chan - San Jose CA, US
Bradley L. Taylor - San Jose CA, US
Nabeel Shirazi - San Jose CA, US

Xilinx, Inc. - San Jose CA

G06F 9/455

703 28

Various embodiments of a co-simulation system are disclosed. In one embodiment, a data processing arrangement executes a simulator that simulates a first block of an electronic circuit design. A first clock source generates a first clock signal, and a second clock source generates a second clock signal. The first and second clock signals are independent one from another, and an operating frequency of the second clock signal is dynamically adjustable from a clock control interface. A programmable logic device (PLD) is configured with logic that includes a co-simulation interface clocked by the first clock signal, a second block of the electronic circuit design that is clocked by the second clock signal, and a synchronizer that controls data transmission between the co-simulation interface and the second block.

7992111, Aug 2, 2011

May 18, 2009

12/467678

Haibing Ma - Superior CO, US
Jingzhao Ou - Sunnyvale CA, US
Chi Bun Chan - San Jose CA, US

Xilinx, Inc. - San Jose CA

G06F 9/45

716103, 716101, 716102, 716104, 716111, 716139

Approaches for processing an electronic circuit design. In one embodiment, the graphical model of an outer subsystem block and an inner subsystem block are translated into a high-level language (HLL) program. The HLL program includes a specification of a first function corresponding to the outer subsystem block and within the specification of the first function a specification of a second function corresponding to the inner subsystem block. The specification of the first function references a parameter of the outer subsystem block and specifies invocation of the second function. The specification of the second function specifies invocation of a third function corresponding to a leaf block in the inner subsystem block. The specification of the first function references a variable corresponding to the parameter, and that variable is referenced by the second or third functions. Execution of the HLL program instantiates a model of the design.

8020127, Sep 13, 2011

Nov 21, 2008

12/275658

Chi Bun Chan - San Jose CA, US
Jingzhao Ou - Sunnyvale CA, US
Jeffrey D. Stroomer - Lafayette CO, US

Xilinx, Inc. - San Jose CA

G06F 9/455
G06F 17/50

716108, 716106, 716132, 716104

A computer-implemented method of circuit design can include receiving clock frequency constraints defining relationships between clock frequencies of a plurality of clock domains of a circuit design specified within a high-level modeling system () and receiving a cost function that is dependent upon the clock frequencies of the plurality of clock domains (). A feasibility result can be determined according to the clock frequency constraints and the cost function (). The feasibility result can indicate whether a clock frequency assignment exists that specifies a clock frequency for each of the plurality of clock domains that does not violate any clock frequency constraint. The feasibility result can be output ().