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Chao Xu

from Westlake Village, CA
Age ~53
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Related to:
Wei Xu, 55Yi Xu, 52Bo Xu, 69Soi Ha Lau, 54Weiwei XuXu Wu, 50Jasmina Cheunglau, 40
Connected to:
Angmai Xu, 69Baoji Xu, 61Baopei Xu, 86Beibei Xu, 41Bingxin Xu, 37Chan Xu, 62Chao Xu, 66Chengkun B Xu, 61Chenxi Xu, 32Chunchun Xu, 35

Chao Xu Phones & Addresses

  • 2827 Westham Cir, Thousand Oaks, CA 91362 (805) 241-1260
  • Westlake Village, CA
  • Oak Park, CA
  • 11543 Twickham Ct, Suwanee, GA 30024 (678) 473-9790
  • Beaverton, OR
  • Ventura, CA
  • Allentown, PA
  • Philadelphia, PA
  • 2827 Westham Cir, Thousand Oaks, CA 91362

Education

Degree: Associate degree or higher

Resumes

Resumes

Chao Xu Photo 1

Vice President Of Technology

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Location:
2827 Westham Cir, Thousand Oaks, CA 91362
Industry:
Semiconductors
Work:
Eta Compute
Vice President of Technology
Inphi Corporation Jul 2007 - Feb 2016
Senior Director, Computing and Storage Platform Engineering
Idt - Integrated Device Technology, Inc. Jun 2003 - Jul 2007
Staff Design Engineer
Accelerant Network Jun 2002 - Jul 2003
Senior Design Engineer
Pmc-Sierra May 2000 - Jun 2002
Mixed-Signal Design Engineer
Education:
University of Pennsylvania 1998 - 2002
Doctorates, Doctor of Philosophy, Electrical Engineering University of Science and Technology of China 1994 - 1997
Masters, Electrical Engineering University of Science and Technology of China 1989 - 1994
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Mixed Signal
Ic
Signal Integrity
Pll
Analog
Serdes
Cmos
Digital Signal Processing
Semiconductors
Integrated Circuit Design
System Architecture
Rf
Pcie
Verilog
Asic
Integrated Circuits
Soc
Hdmi
Application Specific Integrated Circuits
Radio Frequency
Signal Processing
Semiconductor Industry
Phase Locked Loop
Languages:
English
Chao Xu Photo 2

Chao Xu

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Chao Xu Photo 3

Chao Xu

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Publications

Us Patents

Locked-Loop Integrated Circuits Having Speed Tracking Circuits Therein

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US Patent:
7239188, Jul 3, 2007
Filed:
Nov 1, 2005
Appl. No.:
11/264111
Inventors:
Chao Xu - Suwanee GA, US
Al Xuefeng Fang - Suwanee GA, US
Assignee:
Integrated Device Technology, Inc. - San Jose CA
International Classification:
H03L 7/06
US Classification:
327156, 327157
Abstract:
Clock generators include phase-locked and delay-locked loop integrated circuits that support efficient high speed testing of clock frequencies. An integrated circuit device is provided with a clock signal generator having at least one delay element therein that is responsive to a control signal. A speed tracking circuit is also provided. This speed tracking circuit is configured to generate a signal having a measurable characteristic that tracks changes in a property of the control signal that influences a delay of the at least one delay element.

Amplitude And Bandwidth Pre-Emphasis Of A Data Signal

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US Patent:
7327814, Feb 5, 2008
Filed:
Jun 5, 2006
Appl. No.:
11/422252
Inventors:
Chao Xu - Suwanee GA, US
Assignee:
Integrated Device Technology, Inc. - San Jose CA
International Classification:
H04B 1/10
US Classification:
375350, 375295
Abstract:
A data transmitter pre-emphasizes the amplitude and frequency bandwidth of a data signal. A data tap generator delays the data signal to generate multiple data tap signals, each of which is delayed by an integer multiple of a data period. A delay module further delays one of the data tap signals by a delay time that is less than the data period to generate a delayed data signal. The delay time of the delayed data signal determines a frequency bandwidth pre-emphasis for the data signal. A filter module multiplies the amplitudes of the data tap signals and the delayed data signal by coefficients to generate signal components of a pre-emphasized data signal. The coefficients of the filter module determine the amplitude pre-emphasis for the data signal. The filter module sums the signal components to generate the pre-emphasized data signal, which includes both the frequency bandwidth pre-emphasis and the amplitude pre-emphasis.

Current Mode Driver With Constant Voltage Swing

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US Patent:
7405594, Jul 29, 2008
Filed:
Jun 16, 2006
Appl. No.:
11/424779
Inventors:
Chao Xu - Suwanee GA, US
Assignee:
Integrated Device Technology, Inc. - San Jose CA
International Classification:
H03K 19/0175
US Classification:
326 82, 326 83
Abstract:
A current mode driver generates a differential output signal that has a constant voltage swing between a lower voltage level and an upper voltage level. A feedback module determines an intermediate voltage between the lower voltage level and the upper voltage level, compares the intermediate voltage with a reference voltage, and generates a control signal based on a result of the comparison. The current mode driver maintains the voltage swing of the differential output signal at a constant voltage based on the control signal. The differential output signal may have a data signal component and a pre-emphasis signal component.

Multiphase Clock Generator

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US Patent:
7545188, Jun 9, 2009
Filed:
Aug 4, 2006
Appl. No.:
11/462627
Inventors:
Chao Xu - Suwanee GA, US
Al Xuefeng Fang - Suwanee GA, US
Assignee:
Integrated Device Technology, Inc - San Jose CA
International Classification:
H03L 7/06
US Classification:
327157, 327148, 327291
Abstract:
A clock generator generates multiple clock signals based on an input signal and adjusts the phases of the clock signals relative to a phase of the input signal, based on a control signal. The clock generator includes a phase locked loop that includes a phase shift unit. The phase shift unit selects some of the clock signals based on the control signal and generates a feedback signal based on the selected clock signals. The feedback signal has a phase based on the phases of the selected clock signals. The phase locked loop aligns the phase of the feedback signal with the phase of the input signal. In this process, the phase locked loop shifts the phase of each of the clock signals relative to the phase of the input signal.

Comparator With Amplitude And Time Hysteresis

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US Patent:
7714620, May 11, 2010
Filed:
Jun 6, 2006
Appl. No.:
11/422381
Inventors:
Chao Xu - Suwanee GA, US
Assignee:
Integrated Device Technology, Inc. - San Jose CA
International Classification:
H03K 5/22
H03K 5/153
US Classification:
327 63, 327 76, 327 75, 327 78
Abstract:
A comparator generates lower and upper reference voltages to establish an amplitude hysteresis. A first comparator circuit generates a first comparison signal indicating whether an input signal is above the upper reference voltage. A second comparator circuit generates a second comparison signal indicating whether the input signal is below the lower reference voltage. Further, the first and second comparison signals may be low-pass filtered to establish a time hysteresis. A latch is set to a first state if the first control signal indicates the input signal is above the upper reference voltage. The latch is set to a second state if the second control signal indicates the input signal is below the lower reference voltage. In some embodiments, the comparator has a rail-to-rail common mode input voltage range, a low-power mode of operation, and is self-biased to compensate for temperature, voltage, and process characteristics.

System And Method For Testing A Clock Circuit

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US Patent:
7750618, Jul 6, 2010
Filed:
Jul 25, 2006
Appl. No.:
11/459889
Inventors:
Al Xuefeng Fang - Suwanee GA, US
Chao Xu - Suwanee GA, US
Assignee:
Integrated Device Technology, Inc. - San Jose CA
International Classification:
G01R 23/14
US Classification:
324 7641, 324 7648
Abstract:
A test circuit determines whether a frequency of an output clock signal of a clock circuit is above an output threshold frequency. An input clock signal of the clock circuit is set to an elevated frequency that is higher than a specified frequency. A first counter counts the number of clock cycles of the input clock signal in a test interval to within a tolerance of the elevated frequency. The tolerance of the elevated frequency is higher than a tolerance of the specified frequency. A second counter counts the number of clock cycles of a feedback clock signal in the test interval. A comparator determines whether the frequency of the output clock signal is above the output threshold frequency based on the number of clock cycles of the input clock signal and the number of clock cycles of the feedback clock signal.

High Speed Memory Module

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US Patent:
8233304, Jul 31, 2012
Filed:
Jul 17, 2009
Appl. No.:
12/505344
Inventors:
Chao Xu - Agoura Hills CA, US
Assignee:
Inphi Corporation - Westlake Village CA
International Classification:
G11C 5/06
US Classification:
365 63, 365191, 711105
Abstract:
A memory module may include a circuit board connectable to a system memory bus through a plurality of contacts disposed along one edge of the circuit board, the system memory bus having three positions for connecting memory modules. A plurality of memory chips may be mounted on the circuit board. The circuit board may include a plurality of D/Q traces to couple a corresponding plurality of D/Q signals from respective contacts to the plurality of memory chips or to one or more buffer chips that isolate the system memory bus from the memory chips. Each of the plurality of D/Q traces may have a predetermined trace impedance selected to provide a predetermined D/Q signal quality level when the memory module is installed in any of the three positions on the system memory bus and equivalent memory modules are installed in the other two positions.

Load Reduction System And Method For Dimm-Based Memory Systems

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US Patent:
8275936, Sep 25, 2012
Filed:
Sep 21, 2009
Appl. No.:
12/563308
Inventors:
Christopher Haywood - Thousand Oaks CA, US
Gopal Raghavan - Thousand Oaks CA, US
Chao Xu - Thousand Oaks CA, US
Assignee:
Inphi Corporation - Westlake Village CA
International Classification:
G06F 12/00
US Classification:
711105, 711 5, 711154, 36518905
Abstract:
A load reduction system and method for use with memory systems which include one or more DIMMs, each of which includes a circuit arranged to buffer data bytes being written to or read from the DIMM, with the system nominally organized such that the bytes of a given data word are conveyed to the DIMMs via respective byte lanes and stored in a given rank on a given DIMM. The system is arranged such that the DRAMs that constitute a given rank are re-mapped across the available DIMMs plugged into the slots, such that a data word to be stored in a given rank is striped across the available DIMMs, thereby reducing the loading on a given byte lane that might otherwise be present. The system is preferably arranged such that any given byte lane is wired to no more than two of the DIMM slots.
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Chao Xu from Westlake Village, CA, age ~53 Get Report