Chao Li Phones & Addresses
-
San Francisco, CA
-
Millbrae, CA
-
Elk Grove Village, IL
Resumes
Resumes
Chao Li San Jose, CA
View pageWork:
AFFILIATION
Oct 2012 to 2000
Member, Accounting Association, UCSB
ALLEN ASSOCIATES
Santa Barbara, CA
Jul 2013 to Aug 2013
Temporary Accounting Assistant
CIB SECURITY
Sunnyvale, CA
Jun 2011 to Sep 2011
Technician
American Marketing Association
Sep 2009 to May 2010
Member
Oct 2012 to 2000
Member, Accounting Association, UCSB
ALLEN ASSOCIATES
Santa Barbara, CA
Jul 2013 to Aug 2013
Temporary Accounting Assistant
CIB SECURITY
Sunnyvale, CA
Jun 2011 to Sep 2011
Technician
American Marketing Association
Sep 2009 to May 2010
Member
Education:
University of California-Santa Barbara
Santa Barbara, CA
Mar 2013
Bachelor of Art in Economic and Accounting
Ohlone College
Fremont, CA
Sep 2010 to May 2011
Business Administration
Central Michigan University
Mount Pleasant, MI
Jan 2007 to May 2010
Bachelor of Science in Business Administration
Santa Barbara, CA
Mar 2013
Bachelor of Art in Economic and Accounting
Ohlone College
Fremont, CA
Sep 2010 to May 2011
Business Administration
Central Michigan University
Mount Pleasant, MI
Jan 2007 to May 2010
Bachelor of Science in Business Administration
Chao Li Chicago, IL
View pageWork:
School and Personal
Chicago, IL
Aug 2012 to May 2014
Research Student
Motorola - A Google Company
Chicago, IL
2013 to May 2013
Software Development and Test Engineer
Shenyang Alcatel Telecommunication Co. Ltd
Shenyang, CN
Jan 2011 to Apr 2011
Communication Engineering Assistant
IBM
Shenyang, CN
May 2009 to Mar 2010
Internship and Trainee
Chicago, IL
Aug 2012 to May 2014
Research Student
Motorola - A Google Company
Chicago, IL
2013 to May 2013
Software Development and Test Engineer
Shenyang Alcatel Telecommunication Co. Ltd
Shenyang, CN
Jan 2011 to Apr 2011
Communication Engineering Assistant
IBM
Shenyang, CN
May 2009 to Mar 2010
Internship and Trainee
Education:
Shenyang University of Technology
Jun 2011
Bachelor's of Engineering
Illinois Institute of Technology
Chicago, IL
Master of Science in Electrical Engineering
Jun 2011
Bachelor's of Engineering
Illinois Institute of Technology
Chicago, IL
Master of Science in Electrical Engineering
Skills:
Proficient in MATLAB, Protus, Windows, Linux, and also Office software; Programming Language: C/C++, Java, Oracle, python script, SQL; Simulation & synthesis: Cadence, Hspice , VHDL and Verilog code.
Chao Li Santa Barbara, CA
View pageWork:
AFFILIATION
Oct 2012 to 2000
Member, Accounting Association, UCSB
CIB SECURITY
Sunnyvale, CA
Jun 2011 to Sep 2011
Technician
American Marketing Association
Sep 2009 to May 2010
Member
Real Food on Campus
Mount Pleasant, MI
Jun 2007 to Sep 2007
Server
Oct 2012 to 2000
Member, Accounting Association, UCSB
CIB SECURITY
Sunnyvale, CA
Jun 2011 to Sep 2011
Technician
American Marketing Association
Sep 2009 to May 2010
Member
Real Food on Campus
Mount Pleasant, MI
Jun 2007 to Sep 2007
Server
Education:
University of California-Santa Barbara
Santa Barbara, CA
Mar 2013
Bachelor of Art in Economic and Accounting
Ohlone College
Fremont, CA
Sep 2010 to May 2011
Business Administration
Central Michigan University
Mount Pleasant, MI
Jan 2007 to May 2010
Bachelor of Science in Business Administration
Santa Barbara, CA
Mar 2013
Bachelor of Art in Economic and Accounting
Ohlone College
Fremont, CA
Sep 2010 to May 2011
Business Administration
Central Michigan University
Mount Pleasant, MI
Jan 2007 to May 2010
Bachelor of Science in Business Administration
Skills:
MS Word, Excel, Powerpoint, Chinese&English
Business Records
Name / Title
Company / Classification
Phones & Addresses
President
CHAO LI ELECTRICAL, INC
Electrical Contractor
Electrical Contractor
996 Randolph St, San Francisco, CA 94132
(415) 239-9688
(415) 239-9688
MEBOOKS, LLC
Principal
Chao's Family Service
Individual and Family Services, Nsk · Individual/Family Services
Individual and Family Services, Nsk · Individual/Family Services
1474 42 Ave, San Francisco, CA 94122
Publications
Us Patents
Anomaly Detection For An E-Commerce Pricing System
View pageUS Patent:
20220237670, Jul 28, 2022
Filed:
Apr 15, 2022
Appl. No.:
17/721594
Inventors:
- Bentonville AR, US
Elham SHAABANI - Redwood City CA, US
Chao LI - San Carlos CA, US
Matyas A. SUSTIK - San Francisco CA, US
Elham SHAABANI - Redwood City CA, US
Chao LI - San Carlos CA, US
Matyas A. SUSTIK - San Francisco CA, US
International Classification:
G06Q 30/02
G06K 9/62
G06Q 20/20
G06N 20/00
G06Q 10/06
G06K 9/62
G06Q 20/20
G06N 20/00
G06Q 10/06
Abstract:
This application relates to apparatus and methods for identifying anomalies within data, such as pricing data. In some examples, a computing device receives data updates and selects a machine learning model to apply to the data update. The computing device may train the machine learning model with features generated based on historical purchase order data. An anomaly score is generated based on application of the machine learning model. Based on the anomaly score, the data update is either allowed, or denied. In some examples, the computing device re-trains the machine learning model with detected anomalies. In some embodiments, the computing device prioritizes detected anomalies for further investigation. In some embodiments, the computing device identifies the cause of the anomalies by identifying at least one feature that is causing the anomaly.
Multiple Spacer Patterning Schemes
View pageUS Patent:
20230093450, Mar 23, 2023
Filed:
Nov 30, 2022
Appl. No.:
18/072457
Inventors:
- Santa Clara CA, US
Rui CHENG - Santa Clara CA, US
Karthik JANAKIRAMAN - San Jose CA, US
Zubin HUANG - Santa Clara CA, US
Diwakar KEDLAYA - Santa Clara CA, US
Meenakshi GUPTA - San Jose CA, US
Srinivas GUGGILLA - San Jose CA, US
Yung-chen LIN - Gardena CA, US
Hidetaka OSHIO - Tokyo, JP
Chao LI - Santa Clara CA, US
Gene LEE - San Jose CA, US
Rui CHENG - Santa Clara CA, US
Karthik JANAKIRAMAN - San Jose CA, US
Zubin HUANG - Santa Clara CA, US
Diwakar KEDLAYA - Santa Clara CA, US
Meenakshi GUPTA - San Jose CA, US
Srinivas GUGGILLA - San Jose CA, US
Yung-chen LIN - Gardena CA, US
Hidetaka OSHIO - Tokyo, JP
Chao LI - Santa Clara CA, US
Gene LEE - San Jose CA, US
International Classification:
H01L 21/033
H01L 21/311
H01L 21/3213
H01L 21/311
H01L 21/3213
Abstract:
The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.
Methods And Apparatus For Anomaly Detections
View pageUS Patent:
20200380570, Dec 3, 2020
Filed:
May 30, 2019
Appl. No.:
16/427238
Inventors:
- Bentonville AR, US
Elham SHAABANI - Redwood City CA, US
Chao LI - San Carlos CA, US
Matyas A. SUSTIK - San Francisco CA, US
Elham SHAABANI - Redwood City CA, US
Chao LI - San Carlos CA, US
Matyas A. SUSTIK - San Francisco CA, US
International Classification:
G06Q 30/02
G06K 9/62
G06Q 10/06
G06N 20/00
G06Q 20/20
G06K 9/62
G06Q 10/06
G06N 20/00
G06Q 20/20
Abstract:
This application relates to apparatus and methods for identifying anomalies within data, such as pricing data. In some examples, a computing device receives data updates and selects a machine learning model to apply to the data update. The computing device may train the machine learning model with features generated based on historical purchase order data. An anomaly score is generated based on application of the machine learning model. Based on the anomaly score, the data update is either allowed, or denied. In some examples, the computing device re-trains the machine learning model with detected anomalies. In some embodiments, the computing device prioritizes detected anomalies for further investigation. In some embodiments, the computing device identifies the cause of the anomalies by identifying at least one feature that is causing the anomaly.
Methods And Apparatus For Anomaly Detections
View pageUS Patent:
20200380571, Dec 3, 2020
Filed:
May 30, 2019
Appl. No.:
16/427241
Inventors:
- Bentonville AR, US
Elham SHAABANI - Redwood City CA, US
Chao LI - San Carlos CA, US
Matyas A. SUSTIK - San Francisco CA, US
Elham SHAABANI - Redwood City CA, US
Chao LI - San Carlos CA, US
Matyas A. SUSTIK - San Francisco CA, US
International Classification:
G06Q 30/02
G06K 9/00
G06F 17/11
G06Q 10/06
G06N 20/00
G06Q 20/20
G06K 9/00
G06F 17/11
G06Q 10/06
G06N 20/00
G06Q 20/20
Abstract:
This application relates to apparatus and methods for identifying anomalies within data, such as pricing data. In some examples, a computing device receives data updates and selects a machine learning model to apply to the data update. The computing device may train the machine learning model with features generated based on historical purchase order data. An anomaly score is generated based on application of the machine learning model. Based on the anomaly score, the data update is either allowed, or denied. In some examples, the computing device re-trains the machine learning model with detected anomalies. In some embodiments, the computing device prioritizes detected anomalies for further investigation. In some embodiments, the computing device identifies the cause of the anomalies by identifying at least one feature that is causing the anomaly.
Multiple Spacer Patterning Schemes
View pageUS Patent:
20200335338, Oct 22, 2020
Filed:
Mar 17, 2020
Appl. No.:
16/821759
Inventors:
- Santa Clara CA, US
Rui CHENG - Santa Clara CA, US
Karthik JANAKIRAMAN - San Jose CA, US
Zubin HUANG - Santa Clara CA, US
Meenakshi GUPTA - San Jose CA, US
Srinivas GUGGILLA - San Jose CA, US
Yung-chen LIN - Gardena CA, US
Hidetaka OSHIO - Tokyo, JP
Chao LI - Santa Clara CA, US
Gene LEE - San Jose CA, US
Rui CHENG - Santa Clara CA, US
Karthik JANAKIRAMAN - San Jose CA, US
Zubin HUANG - Santa Clara CA, US
Meenakshi GUPTA - San Jose CA, US
Srinivas GUGGILLA - San Jose CA, US
Yung-chen LIN - Gardena CA, US
Hidetaka OSHIO - Tokyo, JP
Chao LI - Santa Clara CA, US
Gene LEE - San Jose CA, US
International Classification:
H01L 21/033
Abstract:
The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.
Multiple Spacer Patterning Schemes
View pageUS Patent:
20200335339, Oct 22, 2020
Filed:
May 5, 2020
Appl. No.:
16/867095
Inventors:
- Santa Clara CA, US
Rui CHENG - Santa Clara CA, US
Karthik JANAKIRAMAN - San Jose CA, US
Zubin HUANG - Santa Clara CA, US
Diwakar KEDLAYA - Santa Clara CA, US
Meenakshi GUPTA - San Jose CA, US
Srinivas GUGGILLA - San Jose CA, US
Yung-chen LIN - Gardena CA, US
Hidetaka OSHIO - Tokyo, JP
Chao LI - Santa Clara CA, US
Gene LEE - San Jose CA, US
Rui CHENG - Santa Clara CA, US
Karthik JANAKIRAMAN - San Jose CA, US
Zubin HUANG - Santa Clara CA, US
Diwakar KEDLAYA - Santa Clara CA, US
Meenakshi GUPTA - San Jose CA, US
Srinivas GUGGILLA - San Jose CA, US
Yung-chen LIN - Gardena CA, US
Hidetaka OSHIO - Tokyo, JP
Chao LI - Santa Clara CA, US
Gene LEE - San Jose CA, US
International Classification:
H01L 21/033
Abstract:
The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.