Zhuang B Wu

University of Southern California

Jan 2014 to 2000
Grader of EE577A-VLSI Systems Design
University of Southern California

Aug 2013 to 2000
Grader of EE557--Computer System Architecture

University of Southern California
Los Angeles, CA
2012 to 2014
Master of Science in Electrical Engineering focus on VLSI (GPA:3.8/4.0)
Beijing University of Aeronautics and Astronautics
2008 to 2012
Bachelor of Science in Electronic and Information Engineering (GPA:3.7/4.0)

- Hardware Description Languages: Verilog and VHDL - Scripting: Perl, Shell,python - Simulation: Modelsim, Cadence NCSim (ASIC) - Synthesis: Xilinx ISE (FPGA), Synopsys DC (ASIC) - Place and Route: Cadence Encounter (ASIC) - Debugging: Chipscope - EDA tools: Cadence Virtuoso, Cadence Spectre - Languages : C/C++

USC

Aug 2013 to 2000
Grader of EE557

University of Southern California
Los Angeles, CA
2012 to 2014
Master of Science in Electrical Engineering
Beijing University of Aeronautics and Astronautics
2008 to 2012
BS in Electronic and Information Engineering

Knowledge in DFT models, ATPG, Fault Simulation, Verification Methodology (VMM/UVM/OVM); Knowledge in RTL Design, ASIC Design Flow, FPGA design, Computer Architecture, Diagnosis and Design of Digital Systems; Hardware Design Languages: Verilog, VHDL, and System Verilog; Software /Script Languages: C /C++/Perl/Python; Simulation /Synthesis Tools: Modelsim, NCsim(ASIC), Cacti, Superscalar/ Xilinx ISE (FPGA), Synopsys DC (ASIC); Place and Route/ Debugging Tools: Cadence Encounter (ASIC)/ Chipscope, and Picoblaze; EDA Tools: Cadence Virtuoso, Cadence Spectre, TetraMax;

University of Southern California
Los Angeles, CA
Jan 2014 to Apr 2014
Grader of EE577A - VLSI System Design
University of Southern California
Los Angeles, CA
Aug 2013 to Dec 2013
Grader of EE557 - Computer Systems Architecture

University of Southern California
Los Angeles, CA
2012 to 2014
MS in Electrical Engineering
Beijing University of Aeronautics and Astronautics
2008 to 2012
BS in Electronic and Information Engineering

Programming Language: Verilog, SystemVerilog for OVM, VMM, UVM Verification, VHDL, Perl, Python, C/C++. Tools: Cadence Virtuoso/NC-Verilog/Encounter, Synopsys Design Compiler/PrimeTime, ModelSim, Questa Sim, Xilinx ISE, PicoBlaze, Proteus.