Zheng T Wu

8386869, Feb 26, 2013

Jun 16, 2009

12/456508

Yu Kou - San Jose CA, US
Zheng Wu - San Jose CA, US

Link—A—Media Devices Corporation - Santa Clara CA

H03M 13/00
H03M 13/25

714746, 714740, 714 49, 341126, 369 4725

A defect portion in a signal is processed by receiving an input signal. A location of a defect portion within the input signal and an amplitude of the defect portion is determined. An adjusted signal is generated by adjusting the amplitude of the defect portion using the determined location of the defect portion and the determined amplitude of the defect portion. Information associated with the adjusted signal is decoded.

8400726, Mar 19, 2013

Jan 27, 2011

13/015492

Zheng Wu - San Jose CA, US
Jason Bellorado - Santa Clara CA, US
Marcus Marrow - Santa Clara CA, US

Link—A—Media Devices Corporation - Santa Clara CA

G11B 5/09

360 32

A target amplitude for an acquisition gain-loop is determined. A tracking gain-loop is configured to adjust a gain of the tracking gain-loop during a data portion of the received signal, wherein the received signal comprises an acquisition portion and the data portion. An acquisition gain-loop is configured to adjust a gain of the acquisition gain-loop during the acquisition portion of the received signal. A detector is configured to detect in the data portion an occurrence of a pattern identical to a portion of the acquisition portion. An amplitude estimation block is configured to compute an amplitude estimate based at least in part on the detected portion. A target amplitude updating block is configured to update the target amplitude based at least in part on the amplitude estimate.

8533576, Sep 10, 2013

Jan 24, 2011

13/012640

Zheng Wu - San Jose CA, US
Jason Bellorado - Santa Clara CA, US
Marcus Marrow - Santa Clara CA, US

SK hynix memory solutions inc. - San Jose CA

H03M 13/00
G06F 11/00

714799

A signal error is determined by obtaining a known property of an expected signal. A signal is received and a signal error is determined based at least in part on the received signal and the known property of the expected signal.

8650459, Feb 11, 2014

Oct 28, 2011

13/284597

Frederick K. H. Lee - Mountain View CA, US
Jason Bellorado - Santa Clara CA, US
Zheng Wu - San Jose CA, US
Marcus Marrow - Santa Clara CA, US

SK hynix memory solutions inc. - San Jose CA

H03M 13/03

714759, 714780, 714794

A log-likelihood ratio (LLR) for a bit bi in a message is determined by generating a first term, including by summing LLRs corresponding to bits in a first codeword having a specified value. The first codeword has a corresponding first message and bit bi of the first message corresponds to a 0. A second term is generated, including by summing LLRs corresponding to bits in a second codeword having the specified value. The second codeword has a corresponding second message and bit bi of the second message corresponds to a 1. The LLR for bit bi in the message is generated based at least in part on the first term and the second term.

20220402140, Dec 22, 2022

Jun 21, 2022

17/845698

- Mountain View CA, US
Stefan Schaal - Mountain View CA, US
Zheng Wu - Albany CA, US

B25J 9/16

A computer-implemented method comprising, receiving data representing a successful trajectory for an insertion task using a robot to insert a connector into a receptacle, performing a parameter optimization process for the robot to perform the insertion task. This parameter optimization includes defining an objective function that measures a similarity of a current trajectory generated with a current set of parameters to the successful trajectory and repeatedly modifying the current set of parameters and evaluating the modified set of parameters according to the objective function until generating a final set of parameters.

20220246171, Aug 4, 2022

Jan 29, 2021

17/162218

- Fremont CA, US
Marcus Marrow - San Jose CA, US
Zheng Wu - Los Altos CA, US

G11B 5/09
H03M 1/12
G06F 13/38

Systems and methods are disclosed for magnetoresistive asymmetry compensation using a hybrid analog and digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing, via the CTFE circuit, first magnetoresistive asymmetry (MRA) compensation on the analog signal to adjust the dynamic range of the analog signal based on an input range of an analog-to-digital converter (ADC). The method may further comprise converting the analog signal to a digital sample sequence via the ADC, and performing, via a digital MRA compensation circuit, second MRA compensation to correct residual MRA in the digital sample sequence. Offset compensation may also be performed in both the analog and digital domains.

20220247418, Aug 4, 2022

Jan 24, 2022

17/582376

- Fremont CA, US
Marcus Marrow - San Jose CA, US
Zheng Wu - Los Altos CA, US

H03M 1/06
H03G 3/30
G11B 5/027
G11B 20/10
G11B 5/012

Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.

20200065262, Feb 27, 2020

Nov 4, 2019

16/672718

- Cupertino CA, US
Marcus Marrow - San Jose CA, US
Zheng Wu - San Jose CA, US

Seagate Technology LLC - Cupertino CA

G06F 13/10
G06F 13/42

Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.