Search

Yuxin Wang

from Sunnyvale, CA
Age ~54
Get Report
Also known as:
Yijiang J Wang, Xin Wang Yu, Wang Yuxin, Caron Coapman
Related to:
Pei C WangWang Kam, 50Ji WangJusong Wang, 46Jason Wong, 58
Connected to:
Adele R Wang, 107Aiyuan Wang, 52Akiet Wang, 74Alene P Wang, 52Amanda K Wang, 46Amei Wang, 61Amity H Wang, 70Amy Wang, 59Anastasia S Wang, 84Ange Wang, 34

Yuxin Wang Phones & Addresses

  • Sunnyvale, CA
  • 45 Lilac Dr, Rochester, NY 14620 (585) 256-0042
  • 713 Richardson Rd, Rochester, NY 14623 (585) 256-0042
  • 248 Quinby Rd, Rochester, NY 14623 (585) 256-0042

Resumes

Resumes

Yuxin Wang Photo 1

Yuxin Wang

View page
Location:
Rochester, New York Area
Industry:
Semiconductors
Yuxin Wang Photo 2

Yuxin Wang

View page
Location:
United States

Publications

Us Patents

On-Chip Bias Voltage Temperature Coefficient Self-Calibration Mechanism

View page
US Patent:
7889575, Feb 15, 2011
Filed:
Sep 22, 2008
Appl. No.:
12/235474
Inventors:
Yuxin Wang - Sunnyvale CA, US
Feng Pan - Fremont CA, US
Byungki Woo - San Jose CA, US
Trung Pham - Fremont CA, US
Khin Htoo - Sunnyvale CA, US
Assignee:
SanDisk Corporation - Milpitas CA
International Classification:
G11C 5/14
US Classification:
36518909, 365211, 36518907, 365196, 36521014, 365207
Abstract:
Techniques and corresponding circuitry for deriving a supply a bias voltage for a memory cell array from a received reference voltage is presented. The circuit includes a voltage determination circuit, which is connected to receive the reference voltage and generate from it the bias voltage, a temperature sensing circuit, and a calibration circuit. The calibration circuit is connected to receive the bias voltage and to receive a temperature indication from the temperature sensing circuit and determine from the bias voltage and temperature indication a compensation factor that is supplied to the voltage determination circuit, which adjusts the bias voltage based upon the compensation factor.

Bandgap Voltage And Temperature Coefficient Trimming Algorithm

View page
US Patent:
8004917, Aug 23, 2011
Filed:
Sep 22, 2008
Appl. No.:
12/235467
Inventors:
Feng Pan - Fremont CA, US
Yuxin Wang - Sunnyvale CA, US
Jonathan H. Huynh - San Jose CA, US
Albert Chang - Santa Clara CA, US
Khin Htoo - Sunnyvale CA, US
Qui Vi Nguyen - San Jose CA, US
Assignee:
SanDisk Technologies Inc. - Plano TX
International Classification:
G11C 7/04
US Classification:
365211, 365212, 365214
Abstract:
A circuit and corresponding method for providing a reference voltage are presented. The circuit includes a current source having a magnitude with positive temperature correlation connected to a node, and a diode element connected between the node and ground, where the node supplies the reference voltage. The circuit also includes a variable resistance connected to receive an input indicative of the circuit temperature and through which the diode element is connected to the node. The value of the variable resistance is adjusted based upon the circuit temperature input. The circuit is useful for application as a peripheral circuitry, such as on a flash or other non-volatile memory and other circuits requiring an on-chip reference voltage source.

Bandgap Voltage And Temperature Coefficient Trimming Algorithm

View page
US Patent:
8228739, Jul 24, 2012
Filed:
Jul 18, 2011
Appl. No.:
13/184778
Inventors:
Feng Pan - Fremont CA, US
Yuxin Wang - Sunnyvale CA, US
Jonathan H. Huynh - San Jose CA, US
Albert Chang - Santa Clara CA, US
Khin Htoo - Sunnyvale CA, US
Qui Vi Nguyen - San Jose CA, US
Assignee:
SanDisk Technologies Inc. - Plano TX
International Classification:
G11C 11/34
US Classification:
36518521, 36518518, 365211, 365212
Abstract:
A circuit and corresponding method for providing a reference voltage are presented. The circuit includes a current source having a magnitude with positive temperature correlation connected to a node, and a diode element connected between the node and ground, where the reference voltage is provided from the node. The circuit also includes a variable resistance connected to receive an input indicative of the circuit temperature and through which the diode element is connected to the node. The value of the variable resistance is adjusted based upon the circuit temperature input. The circuit is useful for application as a peripheral circuitry, such as on a flash or other non-volatile memory and other circuits requiring an on-chip reference voltage source.

Charge Pump With Reduced Energy Consumption Through Charge Sharing And Clock Boosting Suitable For High Voltage Word Line In Flash Memories

View page
US Patent:
8339183, Dec 25, 2012
Filed:
Jul 24, 2009
Appl. No.:
12/509367
Inventors:
Khin Htoo - San Jose CA, US
Feng Pan - Fremont CA, US
Byungki Woo - San Jose CA, US
Trung Pham - Fremont CA, US
Yuxin Wang - Sunnyvale CA, US
Assignee:
SanDisk Technologies Inc. - Plano TX
International Classification:
G05F 1/10
US Classification:
327536, 363 60
Abstract:
A charge pump circuit for generating an output voltage is described. Charge pump circuits typically have two branches. As the clocks supplying the branches of a charge pump circuit alternate, the output of each branch will alternately provide an output voltage, which are then combined to form the pump output. The techniques described here allow charge to be transferred between the two branches, so that as the capacitor of one branch discharges, it is used to charge up the capacitor in the other branch. An exemplary embodiment using a voltage doubler-type of circuit, with the charge transfer between the branches accomplished using a switch controller by a boosted version of the clock signal, which is provided by a one-sided voltage doubler.

Image Sensor Pixel Noise Measurement

View page
US Patent:
20170359532, Dec 14, 2017
Filed:
Jun 10, 2016
Appl. No.:
15/179648
Inventors:
- Santa Clara CA, US
Liping Deng - Cupertino CA, US
Yingkan Lin - San Jose CA, US
Liang Zuo - San Jose CA, US
Yuxin Wang - Sunnyvale CA, US
International Classification:
H04N 5/357
H04N 5/378
Abstract:
An image sensor pixel noise measurement circuit includes a pixel array on an integrated circuit chip. The pixel array includes a plurality of pixels including a first pixel to output a first image data signal, and a second pixel to output a second image data signal. A noise amplification circuit on the integrated circuit chip is coupled to receive the first and second image data signals from the pixel array. The noise amplification circuit is coupled to output an amplified differential noise signal in response to the first and second image data signals received from the pixel array. A fast Fourier transform (FFT) analysis circuit on the integrated circuit chip is coupled to transform the amplified differential noise signal output by the noise amplification circuit from a time domain to a frequency domain to analyze a pixel noise characteristic of the pixel array.
Control profile
Yuxin Wang from Sunnyvale, CA, age ~54 Get Report