Resumes
Resumes
Yucong Tao Phones & Addresses
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13298 Deer Canyon Pl, San Diego, CA 92129 (858) 284-8463
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10589 Caminito Alvarez, San Diego, CA 92126
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7265 Arroyo Grande Rd, San Diego, CA 92129 (858) 484-8117
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Saint Petersburg, FL
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28398 Openfield Loop, Zephyrhills, FL 33543
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Tampa, FL
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Duluth, GA
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13298 Deer Canyon Pl, San Diego, CA 92129
Work
Position:
Professional/Technical
Education
Degree:
Graduate or professional degree
Publications
Us Patents
Dynamically Self-Reconfigurable Daisy-Chain Of Tap Controllers
View pageUS Patent:
20130086441, Apr 4, 2013
Filed:
Sep 30, 2011
Appl. No.:
13/107728
Inventors:
Chang Yong Yang - Fayetteville NC, US
Clint W. Mumford - Apex NC, US
Yucong Tao - San Diego CA, US
Craig E. Borden - Placenta CA, US
Clint W. Mumford - Apex NC, US
Yucong Tao - San Diego CA, US
Craig E. Borden - Placenta CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
G01R 31/3177
G06F 11/25
G06F 11/25
US Classification:
714727, 714E11155
Abstract:
A self-reconfigurable daisy-chain of TAP controllers includes a main TAP controller and one or more auxiliary TAP controllers. The daisy-chain is dynamically self-reconfigurable in that the main TAP controller can configure and reconfigure the daisy-chain multiple times during the testing of a circuit. A data register within the main TAP controller is associated with a special JTAG instruction. This instruction is usable to enable and disable selected individual ones of the auxiliary TAP controllers. If an auxiliary controller is enabled, then it is made a part of the TDI-to-TDO daisy-chain scan path. If the auxiliary controller is disabled, then it is not a part of the daisy-chain scan path. A disabled controller and its registers are not, however, reset. A disabled controller can continue to supply test signals to the circuit under test. Using this mechanism, test time can be reduced by reducing the amount of shifting through slow controllers.
Integrated Circuit Testing With Power Collapsed
View pageUS Patent:
20120216089, Aug 23, 2012
Filed:
Feb 23, 2011
Appl. No.:
13/032732
Inventors:
Wei Chen - San Diego CA, US
Yucong Tao - San Diego CA, US
Matthew L. Severson - San Diego CA, US
Jeffrey R. Gemar - San Diego CA, US
Chang Yong Yang - Fayetteville NC, US
Yucong Tao - San Diego CA, US
Matthew L. Severson - San Diego CA, US
Jeffrey R. Gemar - San Diego CA, US
Chang Yong Yang - Fayetteville NC, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 11/00
H03L 5/00
G01R 31/40
G06F 19/00
H03L 5/00
G01R 31/40
G06F 19/00
US Classification:
714727, 700121, 327333, 32476401, 714E1102
Abstract:
In examples, apparatus and methods are provided for an integrated circuit. The integrated circuit includes a first integrated circuit portion having a main power domain and a second integrated circuit portion having a collapsible power domain. The integrated circuit also has a level shifter having an input coupled to the second circuit portion and an output coupled to the first integrated circuit portion. The level shifter is configured to hold constant the level shifter output when power to the collapsible power domain is collapsed. A quiescent drain current measurement circuit can be coupled to test at least a part of the second integrated circuit portion. A boundary scan register can be coupled between the level shifter output and the first integrated circuit portion. The integrated circuit can also include a power management circuit.
Apparatus And Method For Detecting Clock Tampering
View pageUS Patent:
20140281643, Sep 18, 2014
Filed:
Mar 13, 2013
Appl. No.:
13/801375
Inventors:
- San Diego CA, US
Matthew Scott McGregor - Huntington Beach CA, US
Yucong Tao - San Diego CA, US
Matthew Scott McGregor - Huntington Beach CA, US
Yucong Tao - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 21/50
US Classification:
713340, 713500
Abstract:
Disclosed is a method for detecting clock tampering. In the method a plurality of resettable delay line segments are provided. Resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times. A monotone signal is provided during a clock evaluate time period associated with a clock. The monotone signal is delayed using each of the plurality of resettable delay line segments to generate a respective plurality of delayed monotone signals. The clock is used to trigger an evaluate circuit that uses the plurality of delayed monotone signals to detect a clock fault.
Protection For System Configuration Information
View pageUS Patent:
20140226426, Aug 14, 2014
Filed:
Feb 12, 2013
Appl. No.:
13/765559
Inventors:
- San Diego CA, US
Michael Batenburg - San Diego CA, US
Esin Terzioglu - San Diego CA, US
Yucong Tao - San Diego CA, US
Michael Batenburg - San Diego CA, US
Esin Terzioglu - San Diego CA, US
Yucong Tao - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G11C 5/14
US Classification:
365226
Abstract:
Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (NVM), test cells associated with the NVM are read first. The test cells share a common power supply with the NVM and output read values from the test cells are configured to deviate from values pre-programmed in the test cells when a subnormal read voltage is applied on the common power supply. Thus, by comparing the output read values with the pre-programmed values, it can be determined whether voltage of the common power supply is subnormal, wherein configuration information will be read incorrectly at a subnormal read voltage. If the voltage is subnormal, power up is aborted. Otherwise, power up is allowed to proceed by reading the configuration information from the NVM.
Integrated Circuit Testing With Power Collapsed
View pageUS Patent:
20140223250, Aug 7, 2014
Filed:
Feb 4, 2014
Appl. No.:
14/172292
Inventors:
- San Diego CA, US
Yucong Tao - San Diego CA, US
Matthew L. Severson - San Diego CA, US
Jeffrey R. Gemar - San Diego CA, US
Chang Yong Yang - San Diego CA, US
Yucong Tao - San Diego CA, US
Matthew L. Severson - San Diego CA, US
Jeffrey R. Gemar - San Diego CA, US
Chang Yong Yang - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G01R 31/3177
US Classification:
714727
Abstract:
Provided are apparatus and methods for testing an integrated circuit. In an exemplary method for testing an integrated circuit, a test controller and a power manager are integrated into a main power domain of the integrated circuit. The test controller can be Joint Test Action Group-compatible. An isolation signal is generated using the power manager. The isolation signal can comprise at least one of a freeze signal configured to isolate an input-output port of the integrated circuit, and a clamp signal configured to isolate a functional module of the integrated circuit. The isolation signal can be stored in a boundary scan register controlled with the test controller. The main power domain is isolated from a power-collapsible domain of the integrated circuit with the isolation signal. Power of the power-collapsible domain is collapsed. When power is collapsed, the power-collapsible domain is tested using the test controller and the power manager. The testing of the power-collapsible domain can comprise testing a power supply current. When power to the power-collapsible domain is collapsed, a level shifter output can be held constant to an output level based on a pre-collapse input from the power-collapsible domain.