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Yoshitaka Baba

from Beaverton, OR
Age ~50
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Connected to:
Atsuko Baba, 97Betty R Baba, 93Byron Baba, 71Carlos Baba, 47Dani E Baba, 55Emmanuel A Baba, 70Harry Baba, 100Issa I Baba, 83Jack Baba, 72Jamel R Baba, 35

Yoshitaka Baba Phones & Addresses

  • 11631 Teal Blvd, Beaverton, OR 97007 (503) 524-1848
  • Poughkeepsie, NY
  • New Paltz, NY

Publications

Us Patents

Twin Monos Array For High Speed Application

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US Patent:
7352033, Apr 1, 2008
Filed:
Aug 30, 2005
Appl. No.:
11/215528
Inventors:
Kimihiro Satoh - Portland OR, US
Tomoko Ogura - Hillsboro OR, US
Ki-Tae Park - Hwasung, KR
Nori Ogura - Hillsboro OR, US
Yoshitaka Baba - Beaverton OR, US
Assignee:
Halo LSI Inc. - Hillsboro OR
International Classification:
H01L 29/772
US Classification:
257365, 257324, 257411
Abstract:
The invention provides a metal bit structure of Twin MONOS memory cell with large channel width and its operational method for high-speed applications using a metal bit array.

Referencing Scheme For Trap Memory

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US Patent:
7447077, Nov 4, 2008
Filed:
Aug 7, 2006
Appl. No.:
11/500115
Inventors:
Tomoko Ogura - Hillsboro OR, US
Nori Ogura - Hillsboro OR, US
Seiki Ogura - Hillsboro OR, US
Yoshitaka Baba - Beaverton OR, US
Assignee:
Halo LSI, Inc. - Hillsboro OR
International Classification:
G11C 11/34
US Classification:
3651852, 36518528, 3652101
Abstract:
A reference circuit is described for creating a reference signal using a twin MONOS memory cell. A first portion of the twin MONOS memory cell connects to a charged and floating bit line a current source formed in a second portion of the twin MONOS cell that discharges the charged bit line to form a reference signal for a sense amplifier. The sense amplifier compares the reference signal to a signal from a selected memory cell upon which memory operations are being performed comprising read, erase verify and program verify.

High Speed Operation Method For Twin Monos Metal Bit Array

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US Patent:
7936604, May 3, 2011
Filed:
Aug 30, 2005
Appl. No.:
11/215418
Inventors:
Tomoko Ogura - Hillsboro OR, US
Nori Ogura - Hillsboro OR, US
Seiki Ogura - Hillsboro OR, US
Tomoya Saito - Beaverton OR, US
Yoshitaka Baba - Beaverton OR, US
Assignee:
Halo LSI Inc. - Hillsboro OR
International Classification:
G11C 11/34
US Classification:
36518505, 36518511, 36518517, 36518518, 36518524, 36518526, 36518533
Abstract:
The present invention provides a novel operational method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.

High Speed Operation Method For Twin Monos Metal Bit Array

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US Patent:
8174885, May 8, 2012
Filed:
May 2, 2011
Appl. No.:
13/068066
Inventors:
Tomoko Ogura - Hillsboro OR, US
Nori Ogura - Hillsboro OR, US
Seiki Ogura - Hillsboro OR, US
Tomoya Saito - Beaverton OR, US
Yoshitaka Baba - Beaverton OR, US
Assignee:
Halo LSI Inc. - Hillsboro OR
International Classification:
G11C 11/34
US Classification:
36518505, 36518511, 36518517, 36518518, 3651852, 36518521, 36518524, 36518526, 36518529, 36518533
Abstract:
The present invention provides a novel read method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell. teh.

Twin Monos Array For High Speed Application

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US Patent:
8633544, Jan 21, 2014
Filed:
Mar 31, 2008
Appl. No.:
12/079966
Inventors:
Kimihiro Satoh - Portland OR, US
Tomoko Ogura - Hillsboro OR, US
Ki-Tae Park - Hwasung, KR
Nori Ogura - Hillsboro OR, US
Yoshitaka Baba - Beaverton OR, US
Assignee:
Halo LSI, Inc. - Hillsboro OR
International Classification:
H01L 29/772
US Classification:
257365, 257324, 257411, 257756, 257E23151, 257E23164
Abstract:
A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.

Twin Monos Array For High Speed Application

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US Patent:
20140133244, May 15, 2014
Filed:
Jan 20, 2014
Appl. No.:
14/158971
Inventors:
- Hillsboro OR, US
Tomoko Ogura - Hillsboro OR, US
Ki-Tae Park - Hwaesung, KR
Nori Ogura - Hillsboro OR, US
Yoshitaka Baba - Beaverton OR, US
Assignee:
Halo LSI, Inc. - Hillsboro OR
International Classification:
G11C 16/08
H01L 29/792
G11C 16/04
US Classification:
36518518, 257326
Abstract:
A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.

Twin Monos Array For High Speed Application

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US Patent:
20140133245, May 15, 2014
Filed:
Jan 20, 2014
Appl. No.:
14/158974
Inventors:
- Hillsboro OR, US
Tomoko Ogura - Hillsboro OR, US
Ki-Tae Park - Hwaesung, KR
Nori Ogura - Hillsboro OR, US
Yoshitaka Baba - Beaverton OR, US
Assignee:
Halo LSI, Inc. - Hillsboro OR
International Classification:
G11C 16/16
US Classification:
36518533
Abstract:
A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.
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Yoshitaka Baba from Beaverton, OR, age ~50 Get Report