Changyong Xiao

8617996, Dec 31, 2013

Jan 10, 2013

13/738435

- Grand Cayman, KY
Honglian Shen - Malta NY, US
Changyong Xiao - Mechanicville NY, US

GLOBALFOUNDRIES Inc. - Grand Cayman

H01L 21/311

438700, 438587, 257E21377

Methods for removal of fins from a semiconductor structure are provided. A fin liner is applied to the fins. The fin liner is then removed from the fins that are to be removed. The fin liner is of a material that is selective compared to the semiconductor fins. Hence, the fins can be removed without significant damage to the fin liner. The subsets of fins that are to be removed are then removed, while the fin liner protects the adjacent fins that are to be kept.

20160315084, Oct 27, 2016

Apr 21, 2015

14/691960

- Grand Cayman, KY
HongLiang SHEN - Ballston Lake NY, US
Changyong XIAO - Mechanicville NY, US
Jianhua YIN - Mechanicville NY, US
Jie CHEN - Mechanicville NY, US
Jin Ping LIU - Ballston Lake NY, US
Hong YU - Rexford NY, US
Zhenyu HU - Clifton Park NY, US
Lan YANG - Ballston Lake NY, US

GLOBALFOUNDRIES INC. - Grand Cayman

H01L 27/092
H01L 29/10
H01L 21/8238

There is set forth herein in one embodiment a semiconductor structure having a first region and a second region. The first region can include fins of a first fin height and the second region can include fins of a second fin height.

20160315172, Oct 27, 2016

Apr 24, 2015

14/695411

- Grand Cayman, KY
Changyong Xiao - Mechanicville NY, US
Min-hwa Chi - Malta NY, US

H01L 29/66
H01L 27/088
H01L 29/78
H01L 29/08

Fin field-effect transistor (FinFET) devices and methods of forming the same are provided herein. In an embodiment, a FinFET device includes a semiconductor substrate having a plurality of fins disposed in parallel relationship. A first insulator layer overlies the semiconductor substrate, with the fins extending through and protruding beyond the first insulator layer to provide exposed fin portions. A gate electrode structure overlies the exposed fin portions and is electrically insulated from the fins by a gate insulating layer. Epitaxially-grown source regions and drain regions are disposed adjacent to the gate electrode structure. The epitaxially-grown source regions and drain regions have an asymmetric profile along a lateral direction perpendicular to a length of the fins.

20160155799, Jun 2, 2016

Jan 20, 2016

15/002000

- Grand Cayman, KY
Changyong XIAO - Mechanicville NY, US
Xiang HU - Clifton Park NY, US

GLOBALFOUNDRIES Inc. - Grand Cayman

H01L 29/06
H01L 29/20
H01L 29/161
H01L 27/092
H01L 29/16

A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

20160126336, May 5, 2016

Oct 29, 2014

14/527250

- Grand Cayman, KY
Changyong XIAO - Mechanicville NY, US
Min-hwa CHI - Malta NY, US

H01L 29/66
H01L 29/49
H01L 29/423
H01L 21/311
H01L 29/417

Processes for forming merged CA/CB constructs and the resulting devices are disclosed. Embodiments include providing a replacement metal gate (RMG) between first and second sidewall spacers surrounded by an insulator on a substrate, the RMG having a dielectric layer directly on the first and second sidewall spacers and having metal on the dielectric layer; providing an oxide layer over the insulator, the first and second sidewall spacers, and the RMG; forming a source/drain contact hole through the oxide layer and the insulator, adjacent to the first sidewall spacer; forming a gate contact hole through the oxide layer over the source/drain contact hole and extending to the metal of the RMG; enlarging the source/drain contact hole to the metal of the RMG; and filling the enlarged source/drain contact hole and gate contact hole with metal.

20160049400, Feb 18, 2016

Oct 27, 2015

14/924486

- Grand Cayman, KY
Changyong XIAO - Mechanicville NY, US
Yiqun LIU - Clifton Park NY, US
Dina H. TRIYOSO - Mechanicville NY, US
Rohit PAL - Mechanicville NY, US

GLOBALFOUNDRIES Inc. - Grand Cayman

H01L 27/092

A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

20160049468, Feb 18, 2016

Aug 11, 2015

14/823319

- Grand Cayman, KY
Changyong Xiao - Mechanicville NY, US
Hongliang Shen - Ballston Lake NY, US

H01L 29/06
H01L 27/088

An integrated circuit product is disclosed that includes a plurality of trenches in a semiconducting substrate that define first, second and third fins, wherein the fins are side-by-side, and wherein the second fin is positioned between the first and third fins, a layer of insulating material in the plurality of trenches such that a desired height of the first, second and third fins is positioned above an upper surface of the layer of insulating material, a recess defined in the second fin that at least partially defines a cavity in the layer of insulating material, an SDB isolation structure in the cavity on the recessed portion of the second fin, wherein the SDB isolation structure has an upper surface that is above the upper surface of the layer of insulating material, and a gate structure for a transistor positioned above the SDB isolation structure.

20150380409, Dec 31, 2015

Jun 26, 2014

14/315885

- Grand Cayman, KY
Changyong XIAO - Mechanicville NY, US
Yiqun LIU - Clifton Park NY, US
Dina H. TRIYOSO - Mechanicville NY, US
Rohit PAL - Mechanicville NY, US

GLOBALFOUNDRIES INC. - Grand Cayman

H01L 27/092
H01L 21/321
H01L 21/265
H01L 21/8238
H01L 21/324

A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.