Wing Yiu Wong

6674479, Jan 6, 2004

Jan 7, 2000

09/478793

Val Cook - Shingle Springs CA
Kam Leung - El Dorado Hills CA
Wing Hang Wong - Folsom CA

Intel Corporation - Santa Clara CA

H04N 701

348453, 348488, 382165, 345600

A method and circuit are provided for color space conversion of Y (luminance) and UV (chrominance) components from a planar YUV 4:2:0 format to an interleaved, or packed YUV 4:2:2 format, and from an interleaved, or packed YUV 4:2:2 format to a planar YUV 4:2:0 format. The method for both conversions includes reading source data, interpolating the sampled YUV component values, and performing a pass to thereby write the converted YUV component values in three passes, one pass for all values of the respective YUV components.

6731297, May 4, 2004

Jan 11, 2000

09/885253

Kam Leung - El Dorado Hills CA
Val G. Cook - Shingle Springs CA
Peter L. Doyle - El Dorado Hills CA
Wing Hang Wong - Folsom CA

Intel Corporation - Santa Clara CA

G09G 500

345582, 345589

A machine readable storage media containing executable program instructions which when executed cause a digital processing system to seta plurality of operands and operators. A plurality of texture maps are sent to a processor for texture compositing. Operands are selected for a texture operation. A first logic is used wherein if the circulation of blend stages is equal to a number of blend stages, then a color saturation is performed, and a second logic that if the circulation number of blend stages does not equal the number of blend stages then at least one operand is selected for another texture compositing operation.

7280113, Oct 9, 2007

Jun 30, 2000

09/609274

Kam Leung - El Dorado Hills CA, US
Val G. Cook - Shingle Springs CA, US
Peter L. Doyle - El Dorado Hills CA, US
Wing Hang Wong - Folsom CA, US

Intel Corporation - Santa Clara CA

G09G 5/00

345582, 345581, 345586, 345589, 345592

A machine readable storage media containing executable program instructions which when executed cause a digital processing system to seta plurality of operands and operators. A plurality of texture maps are sent to a processor for texture compositing. Operands are selected for a texture operation. A first logic is used wherein if the circulation of blend stages is equal to a number of blend stages, then a color saturation is performed, and a second logic that if the circulation number of blend stages does not equal the number of blend stages then at least one operand is selected for another texture compositing operation.

7802146, Sep 21, 2010

Jun 7, 2007

11/759847

Allan Wong - Folsom CA, US
Ke Yin - El Dorado Hills CA, US
Naveen Matam - Rancho Cordova CA, US
Anthony Babella - Salida CA, US
Wing Hang Wong - Folsom CA, US

Intel Corporation - Santa Clara CA

G06F 11/00

714 40, 714 27, 712227

Provided are a method and system for loading test data into execution units in a graphics card to test the execution units. Test instructions are loaded into a cache in a graphics module comprising multiple execution units coupled to the cache on a bus during a design test mode. The cache instructions are concurrently transferred to an instruction queue of each execution unit to concurrently load the cache instructions into the instruction queues of the execution units. The execution units concurrently execute the cache instructions to fetch test instructions from the cache to load into memories of the execution units and execute during the design test mode.

20040119886, Jun 24, 2004

Dec 10, 2003

10/732561

Val Cook - Shingle Springs CA, US
Kam Leung - El Dorado Hills CA, US
Wing Wong - Folsom CA, US

Intel Corporation

H04N011/20

348/453000

A method and circuit are provided for color space conversion of Y (luminance) and UV (chrominance) components from a planar YUV 4:2:0 format to an interleaved, or packed YUV 4:2:2 format, and from an interleaved, or packed YUV 4:2:2 format to a planar YUV 4:2:0 format. The method for both conversions includes reading source data, interpolating the sampled YUV component values, and performing a pass to thereby write the converted YUV component values in three passes, one pass for all values of the respective YUV components.

20070291045, Dec 20, 2007

Aug 24, 2007

11/895382

Kam Leung - El Dorado Hills CA, US
Val Cook - Shingle Spring CA, US
Peter Doyle - El Dorado Hills CA, US
Wing Wong - Folsom CA, US

G09G 5/00

345582000

A machine readable storage media containing executable program instructions which when executed cause a digital processing system to set a plurality of operands and operators. A plurality of texture maps are sent to a processor for texture compositing. Operands are selected for a texture operation. A first logic is used wherein if the circulation of blend stages is equal to a number of blend stages, then a color saturation is performed, and a second logic that if the circulation number of blend stages does not equal the number of blend stages then at least one operand is selected for another texture compositing operation.

42108292, Jul 1, 1980

Oct 2, 1978

5/947521

Thomas S. W. Wong - San Francisco CA
Wing Y. Wong - Sunnyvale CA
Edwin M. W. Chow - Sunnyvale CA

National Semiconductor Corporation - Santa Clara CA

H03K 1760
H03K 508

307296R

A power up circuit for an associated digital circuit is disclosed which prevents noise from falsely resetting the associated digital circuit after completion of the powering up function. The power up circuit has a series connection of a first capacitor and a high impedance coupled between the power supply and ground. The high impedance is connected in parallel with the source and drain electrodes of an enhancement type field effect transistor. The node of the high impedance and the first capacitor is connected to an inverting amplifier which produces an inverted output after the input signal falls to a threshold potential. The output of the inverting amplifier is connected to the gate of the field effect transistor and to a second capacitor which is connected to ground. The output of the inverting amplifier is applied to the reset line of the associated digital circuit to cause resetting of the digital circuit upon the connection of the power supply to the digital circuit. After powering up, the field effect transistor is biased on by the output of the inverting amplifier.

20210100065, Apr 1, 2021

Aug 24, 2020

17/001563

- Mountain View CA, US
Rolando Willcox Esparza - San Francisco CA, US
George Liu - Taipei City, TW
Wing Tung Wong - Mountain View CA, US
Frédéric Heckmann - Taipei City, TW
Vivian W. Tang - Mountain View CA, US

Google LLC - Mountain View CA

H04W 88/08
H05K 1/02
H05K 7/20
H05K 7/14
H01Q 5/307

This document describes an access point device and associated systems and methods. The techniques and systems include an access point device that includes a housing with an antenna carrier, a circuit board assembly, a heat sink, and a heat shield positioned within the housing. The housing includes a top housing member connected to a bottom housing member. The top housing member includes a concave-down top-end portion connected to a generally cylindrical vertical wall via rounded corners. The antenna carrier supports multiple antennas positioned proximate to an inner surface of the vertical wall. The heat sink is positioned between the antenna carrier and the circuit board assembly. The circuit board assembly is positioned between the heat shield and the heat sink, and the heat shield is positioned between the circuit board assembly and the bottom housing member.