Resumes
Resumes
Senior Staff Engineer
View pageLocation:
2226 Annapolis Dr, Fremont, CA 94539
Industry:
Semiconductors
Work:
Synopsys
Senior Staff Engineer
Virage Logic May 1999 - Sep 2010
Director, Test Chip Design and Integration Methodology
Lattice Semiconductor Aug 1993 - May 1999
Cae Manager
Altera Sep 1992 - Aug 1993
Senior Engineer
Fujitsu Jul 1990 - Sep 1992
Senior Engineer
Senior Staff Engineer
Virage Logic May 1999 - Sep 2010
Director, Test Chip Design and Integration Methodology
Lattice Semiconductor Aug 1993 - May 1999
Cae Manager
Altera Sep 1992 - Aug 1993
Senior Engineer
Fujitsu Jul 1990 - Sep 1992
Senior Engineer
Education:
Santa Clara University Sep 1995 - Mar 1998
Santa Clara University Sep 1990 - Jun 1995
Master of Science, Masters Stanford University Sep 1983 - Jun 1987
Bachelors, Bachelor of Science, Electrical Engineering
Santa Clara University Sep 1990 - Jun 1995
Master of Science, Masters Stanford University Sep 1983 - Jun 1987
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Asic
Eda
Static Timing Analysis
Fpga
Verilog
Semiconductors
Physical Design
Cadence
Mixed Signal
Physical Verification
Simulations
Soc
P&R
Microprocessors
Analog
Tcl
Logic Synthesis
Silicon
Drc
Calibre
Altera
Place and Route
Modeling
Vlsi
Eda
Static Timing Analysis
Fpga
Verilog
Semiconductors
Physical Design
Cadence
Mixed Signal
Physical Verification
Simulations
Soc
P&R
Microprocessors
Analog
Tcl
Logic Synthesis
Silicon
Drc
Calibre
Altera
Place and Route
Modeling
Vlsi
Interests:
Boating
Cooking
Investing
Outdoors
Sweepstakes
Electronics
Home Improvement
Reading
Crafts
Gourmet Cooking
Sports
Home Decoration
Cooking
Investing
Outdoors
Sweepstakes
Electronics
Home Improvement
Reading
Crafts
Gourmet Cooking
Sports
Home Decoration
Languages:
Mandarin
Integration Methodology Manager
View pageLocation:
San Francisco, CA
Industry:
Semiconductors
Work:
Virage Logic
Integration Methodology Manager
Integration Methodology Manager