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William M Sablinski

from Beacon, NY
Deceased

William Sablinski Phones & Addresses

  • 4 Miller St, Beacon, NY 12508 (845) 831-2481
  • 8 Miller St, Beacon, NY 12508
  • 4 Miller St, Beacon, NY 12508

Work

Position: Personal Care and Service Occupations

Education

Degree: Graduate or professional degree

Publications

Us Patents

High Density Column Grid Array Connections And Method Thereof

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US Patent:
6429388, Aug 6, 2002
Filed:
May 3, 2000
Appl. No.:
09/564110
Inventors:
Mario J. Interrante - New Paltz NY
Brenda Peterson - Wappingers Falls NY
Sudipta K. Ray - Wappingers Falls NY
William E. Sablinski - Beacon NY
Amit K. Sarkhel - Endicott NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01R 909
US Classification:
174261, 439 65, 439 66, 439 75
Abstract:
The present invention relates generally to a new semiconductor chip carrier connections, where the chip carrier and the second level assembly are made by a surface mount technology. More particularly, the invention encompasses surface mount technologies, such as, Ball Grid Array (BGA), Column Grid Array (CGA), to name a few, where the surface mount technology comprises essentially of a non-solder metallic connection, such as, a copper connection. The present invention is also related to Column Grid Array structures and process thereof.

Temporary Attach Article And Method For Temporary Attach Of Devices To A Substrate

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US Patent:
6518674, Feb 11, 2003
Filed:
Mar 13, 2001
Appl. No.:
09/805596
Inventors:
Mario J. Interrante - New Paltz NY
Thomas E. Lombardi - Poughkeepsie NY
Frank L. Pompeo - Montgomery NY
William E. Sablinski - Beacon NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2348
US Classification:
257772, 257779, 438108, 438616, 22818022
Abstract:
A temporary attach article of a first component to a second component which includes a first component having a first volume of a fusible material; a second component having a second volume of fusible material; and the first and second components being joined together through the first and second volumes of fusible material, wherein the first volume of fusible material has a melting point higher than a melting point of the second volume of fusible material so that the first and second components may be joined together without melting of the first volume of fusible material and wherein the second volume of fusible material is 5 to 20% of the first volume of fusible material. Also disclosed is a method for temporary attach of devices to an electronic substrate.

Interconnection Process For Module Assembly And Rework

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US Patent:
6574859, Jun 10, 2003
Filed:
Feb 16, 2001
Appl. No.:
09/785787
Inventors:
Shaji Farooq - Hopewell Junction NY
Mario J. Interrante - New Paltz NY
Sudipta K. Ray - Wappingers Falls NY
William E. Sablinski - Beacon NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 336
US Classification:
29830
Abstract:
An interconnection structure and methods for making and detaching the same are presented for column and ball grid array (CGA and BGA) structures by using a transient solder paste on the electronic module side of the interconnection that includes fine metal powder additives to increase the melting point of the solder bond. The metal powder additives change the composition of the solder bond such that the transient melting solder composition does not completely melt at temperatures below +230Â C. and detach from the electronic module during subsequent ref lows. A PbâSn eutectic with a lower melting point is used on the opposite end of the interconnection structure. In the first method a transient melting solder paste is applied to the I/O pad of an electronic module by means of a screening mask. Interconnect structures are then bonded to the I/O pad. In a second method, solder preforms in a composition of the transient melting solder paste are wetted onto electronic module I/O pads and interconnect columns or balls are then bonded.

Emi Shielding For Semiconductor Chip Carriers

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US Patent:
6740959, May 25, 2004
Filed:
Aug 1, 2001
Appl. No.:
09/921062
Inventors:
David James Alcoe - Vestal NY
Jeffrey Thomas Coffin - Pleasant Valley NY
Michael Anthony Gaynes - Vestal NY
Harvey Charles Hamel - Poughkeepsie NY
Mario J. Interrante - New Paltz NY
Brenda Lee Peterson - Wappingers Falls NY
Megan J. Shannon - Wappingers Falls NY
William Edward Sablinski - Beacon NY
Christopher Todd Spring - Wappingers Falls NY
Randall Joseph Stutzman - Vestal NY
Renee L. Weisman - Poughkeepsie NY
Jeffrey Allen Zitz - Poughkeepsie NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 23552
US Classification:
257659, 257660, 257661, 257662
Abstract:
Electronic packages incorporating EMI shielding, and particularly semiconductor devices which incorporate semiconductor chip-carrier structures having grounded bands embedded therein which are adapted to reduce outgoing and incident EMI emissions for high-speed switching electronic packages.

Optoelectronic Package Structure And Process For Planar Passive Optical And Optoelectronic Devices

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US Patent:
6827505, Dec 7, 2004
Filed:
Dec 16, 2002
Appl. No.:
10/320844
Inventors:
Subhash L. Shinde - Cortlandt Manor NY
L. Wynn Herron - New Paltz NY
Mario J. Interrante - New Paltz NY
How T. Lin - Vestal NY
Steven P. Ostrander - Poughkeepsie NY
Sudipta K. Ray - Wappingers Falls NY
William E. Sablinski - Beacon NY
Hilton Toy - Hopewell Junction NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G02B 636
US Classification:
385 92, 385 88, 385 89
Abstract:
An optical-electronic package for an electronic device provides electrical connections to the electronic device and optical fiber connections to the electronic device. The package includes a high thermal conductivity base which has a pedestal to support and provide heat transfer connection to the electronic device. A seal band is formed on the base and a casing is bonded to the seal band. The casing has side feedthroughs for the electrical connections from the electronic device, and the casing has top feedthroughs or grooves for the optical fiber connections from the electronic device. A lid is hermetically sealed to the top of the casing. The lid has retractable means for forming a bend in the optical fibers to provide strain relief when the lid is placed on the casing. The retractable means for forming a bend in the optical fibers is retractable once the lid is sealed on the casing.

Structure And Method For Lead Free Solder Electronic Package Interconnections

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US Patent:
6854636, Feb 15, 2005
Filed:
Dec 6, 2002
Appl. No.:
10/314498
Inventors:
Mukta G. Farooq - Hopewell Junction NY, US
Mario Interrante - New Paltz NY, US
William Sablinski - Beacon NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
B23K031/00
US Classification:
22818022, 228246
Abstract:
An electronic package having a solder interconnect liquidus temperature hierarchy to limit the extent of the melting of the C4 solder interconnect during subsequent second level join/assembly and rework operations. The solder hierarchy employs the use of off-eutectic solder alloys of Sn/Ag and Sn/Cu with a higher liquidus temperature for the C4 first level solder interconnections, and a lower liquidus temperature alloy for the second level interconnections. When the second level chip carrier to PCB join/assembly operations occur, the chip to chip carrier C4 interconnections do not melt completely. They continue to have a certain fraction of solids, and a lower fraction of liquids, than a fully molten alloy. This provides reduced expansion of the solder join and consequently lower stresses on the C4 interconnect.

Solder Hierarchy For Lead Free Solder Joint

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US Patent:
6892925, May 17, 2005
Filed:
Sep 18, 2002
Appl. No.:
10/246282
Inventors:
Mario Interrante - New Paltz NY, US
Mukta G. Farooq - Hopewell Junction NY, US
William Sablinski - Beacon NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
B23K035/14
H01L021/44
US Classification:
228 563, 228245, 228246, 438612
Abstract:
A lead free solder hierarchy for use in the second level solder connection of electronic components such as joining an electronic module to a circuit board. An off-eutectic solder concentration of SnCu or SnAg is used for the module side connection. This off-eutectic solder contains sufficient intermetallics to provide the module side connection with a robust second level assembly and rework process. The off-eutectic composition provides an inter-metallic phase structure in the module side fillet during assembly. The inter-metallic phase structure eliminates problems of tilt and collapse during second level assembly and aids in rework by providing a more cohesive joint allowing removal of the columns from the board without simultaneous removal from the module.

Method For Forming Robust Solder Interconnect Structures By Reducing Effects Of Seed Layer Underetching

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US Patent:
6995084, Feb 7, 2006
Filed:
Mar 17, 2004
Appl. No.:
10/708649
Inventors:
Kamalesh K. Srivastava - Wappingers Falls NY, US
Subhash L. Shinde - Courtlandt Manor NY, US
Tien-Jen Cheng - Bedford NY, US
Sarah H. Knickerbocker - Hopewell Junction NY, US
Roger A. Quon - Rhinebeck NY, US
William E. Sablinski - Beacon NY, US
Julie C. Biggs - Wappingers Falls NY, US
David E. Eichstadt - Park Ridge IL, US
Jonathan H. Griffith - Lagrangeville NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/44
US Classification:
438613, 438614
Abstract:
A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.
William M Sablinski from Beacon, NYDeceased Get Report