William Mark Mckee

6396088, May 28, 2002

Jul 19, 2001

09/909191

Goro Kitsukawa - Hinode-machi, JP
Takesada Akiba - Tachikawa, JP
Hiroshi Otori - Ome, JP
William R. McKee - Plano TX
Jeffrey E. Koelling - Dallas TX
Troy H. Herndon - Richardson TX

Hitachi, Ltd. - Tokyo

H01L 2716

257207, 257202, 257307

A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

6461955, Oct 8, 2002

Mar 9, 2000

09/521325

Robert Tsu - Plano TX
William R. Mckee - Plano TX

Texas Instruments Incorporated - Dallas TX

H01L 214763

438618, 438622, 438637, 438694, 438738, 438745

A dual damascene process. After the via etch, a via protect layer ( ) is deposited in the via ( ). The via protect layer ( ) comprises a material that has a dry etch rate at least equal to that of the IMD ( ) and a wet etch rate that is approximately 100 times that of the IMD ( ) or greater. Exemplary materials include PSG, BPSG, and HSQ. The trench pattern ( ) is formed and both the via protect layer ( ) and IMD ( ) are etched. The remaining portions of the via protect layer ( ) are then removed prior to forming the metal layer ( ).

6512257, Jan 28, 2003

Apr 11, 2002

10/120872

Goro Kitsukawa - Tokyo, JP
Takesada Akiba - Tokyo, JP
Hiroshi Otori - Tokyo, JP
William R. McKee - Plano TX
Jeffrey E. Koelling - Dallas TX
Troy H. Herndon - Richardson TX

Hitachi, Inc. - Tokyo
Texas Instruments Incorporated - Dallas TX

H01L 31119

257296, 257287, 257307, 36518905, 36518912, 365207, 365149

A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

6528888, Mar 4, 2003

Feb 2, 2001

09/776212

Chih-Chen Cho - Richardson TX
Jeffrey A. McKee - Grapevine TX
William R. McKee - Plano TX
Isamu Asano - Iruma, JP
Robert Y. Tsu - Plano TX

Texas Instruments Incorporated - Dallas TX

H01L 2348

257775, 257306, 257750, 257773

An integrated circuit. The circuit includes a memory cell array including wordlines formed on a substrate and bitlines and capacitors formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.

6559050, May 6, 2003

Oct 19, 2000

09/691907

William R. McKee - Plano TX
Dirk N. Anderson - Plano TX
Wei Lee - Plano TX

Texas Instruments Incorporated - Dallas TX

H01L 2144

438656, 438629, 438648, 438666, 438672, 438685

A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride (WSi N ) region providing the interface between the tungsten conducting plug and the substrate (silicon) layer. The interface region is formed providing a nitrided surface layer over the exposed dielectric surfaces and the exposed substrate surface (i. e. , exposed by a via in the dielectric layer) prior to the formation of tungsten/tungsten nitride layer filling the via. The structure is annealed forming a tungsten conducting plug with a tungsten-silicon-nitride interface between the conducting plug and the substrate. According to another embodiment, a tungsten nitride surface layer is formed over the nitrided surface layer prior to the formation of a tungsten layer to fill the via. According to another embodiment, a silicon surface layer is applied to the exposed surface of the dielectric layer and to the exposed surface of the substrate prior to formation of the nitrided surface layer. A layer of tungsten, tungsten/tungsten nitride, or tungsten nitride is formed to fill the via.

6653676, Nov 25, 2003

Jul 30, 2001

09/918228

Robert Tsu - Plano TX
Isamu Asano - Iruma, JP
Shinpei Iijima - Tokyo, JP
William R. McKee - Plano TX

Texas Instruments Incorporated - Dallas TX

H01L 27108

257296, 257301, 257306, 257310, 257311

The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode adjacent an insulating region. This base electrode can comprise either polysilicon or a metal. A layer of a first material, such as a siliciding metal, is formed over the base electrode as well as the adjacent insulating region. A self-aligned capacitor electrode can then be formed by reacting the first material with the base electrode and removing unreacted portions of the first material from the insulating region. The capacitor is then completed by forming a dielectric layer over the self-aligned capacitor electrode and a second capacitor electrode over the dielectric layer.

6815742, Nov 9, 2004

Dec 5, 2003

10/728682

Goro Kitsukawa - Tokyo, JP
Takesada Akiba - Tokyo, JP
Hiroshi Otori - Tokyo, JP
William R. McKee - Plano TX
Jeffrey E. Koelling - Dallas TX
Troy H. Herndon - Richardson TX

Hitachi, Ltd. - Tokyo
Texas Instruments Incorporated - Dallas TX

H01L 31112

257287, 257296, 257307, 257333

A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

6831317, Dec 14, 2004

Dec 10, 2002

10/315307

Goro Kitsukawa - Hinode-machi, JP
Takesada Akiba - Tachikawa, JP
Hiroshi Otori - Ome, JP
William R. McKee - Plano TX
Jeffrey E. Koelling - Dallas TX
Troy H. Herndon - Richardson TX

Hitachi, Ltd. - Tokyo

H01L 31119

257296, 257202, 257207, 257287, 257304, 257307

A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.