William C Lau

7069371, Jun 27, 2006

Mar 10, 2004

10/798485

Eugene Feng - San Jose CA, US
William Lau - Menlo Park CA, US
Frank Fong-Long Lin - Fremont CA, US

Silicon Storage Technology, Inc. - Sunnyvale CA

G06F 13/14
G06F 13/00

710305, 710105, 711103, 713100

A motherboard of a computer system has a video display port, a reprogrammable non-volatile memory, a controller for the non-volatile memory, and a graphics controller circuit for outputting video signals to the video display port. A wired-OR circuit connects the graphics controller circuit to the controller to the port. Thus, the video display port can be used to output video signals from the computer system to a peripheral video display device, and the video display port can be used as an input port to reprogram the non-volatile memory. The present invention also relates to a non-volatile memory device which has an array of non-volatile memory cells and two ports for communication therewith. A first port receives a first communication protocol and interfaces with the array in the first communication protocol. A second port receives a second communication protocol and converts the second communication protocol into the first communication protocol.

7146442, Dec 5, 2006

Apr 19, 2006

11/407601

Eugene Feng - San Jose CA, US
William Lau - Menlo Park CA, US
Fong-Long Lin - Fremont CA, US

Silicon Storage Technology, Inc. - Sunnyvale CA

G06F 13/00
G06F 3/00

710100, 713 2, 713100

A motherboard of a computer system has a video display port, a reprogrammable non-volatile memory, a controller for the non-volatile memory, and a graphics controller circuit for outputting video signals to the video display port. A wired-OR circuit connects the graphics controller circuit to the controller to the port. Thus, the video display port can be used to output video signals from the computer system to a peripheral video display device, and the video display port can be used as an input port to reprogram the non-volatile memory. The present invention also relates to a non-volatile memory device which has an array of non-volatile memory cells and two ports for communication therewith. A first port receives a first communication protocol and interfaces with the array in the first communication protocol. A second port receives a second communication protocol and converts the second communication protocol into the first communication protocol.

7239170, Jul 3, 2007

Jul 8, 2003

10/614956

Victor Suen - Fremont CA, US
William Lau - Foster City CA, US
Cheng-Gang Kong - Saratoga CA, US

LSI Corporation - Milpitas CA

H03K 17/16
H03K 19/003

326 30, 326 86

Apparatus and methods are provided for improving data exchanges between electronic devices, such as memory controllers and RLDRAMs. An I/O cell includes a signal pad for transferring a first signal to an electronic device coupled thereto and for receiving a second signal from the electronic device. In one aspect, a duty cycle controller is coupled to the signal pad for balancing a duty cycle of the first signal with respect to a clock signal. In another aspect, dynamic switchable termination is coupled to the signal pad for providing termination impedance when the I/O cell is receiving the second signal.

8239813, Aug 7, 2012

Jun 30, 2011

13/173855

Andrey Nikitin - Moscow, RU
Ranko Scepanovic - San Jose CA, US
Igor Kucherenko - Moscow, RU
William Lau - Foster City CA, US
Cheng-Gang Kong - Saratoga CA, US
Hui-Yin Seto - San Jose CA, US
Andrej Zolotykih - Fryazino, RU
Ivan Pavisic - San Jose CA, US
Sandeep Bhutani - Pleasanton CA, US
Aiguo Lu - Pleasanton CA, US
Ilya Lyalin - Moscow, RU

LSI Corporation - Milpitas CA

G06F 17/50
G06F 9/455

716134, 716103, 716107, 716108, 716113, 716131, 716132

A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.

8516425, Aug 20, 2013

Jul 9, 2012

13/544632

Andrey Nikitin - Moscow, RU
Ranko Scepanovic - San Jose CA, US
Igor Kucherenko - Moscow, RU
William Lau - Foster City CA, US
Cheng-Gang Kong - Saratoga CA, US
Hui-Yin Seto - San Jose CA, US
Andrej Zolotykih - Fryazino, RU
Ivan Pavisic - San Jose CA, US
Sandeep Bhutani - Pleasanton CA, US
Aiguo Lu - Pleasanton CA, US
Ilya Lyalin - Moscow, RU

LSI Corporation - Milpitas CA

G06F 17/50

716115, 716126, 716127, 716130, 716131, 716132, 716139, 257508, 257661, 257662

A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.

7996804, Aug 9, 2011

Jan 17, 2008

12/015925

Andrey Nikitin - Moscow, RU
Ranko Scepanovic - San Jose CA, US
Igor Kucherenko - Moscow, RU
William Lau - Foster City CA, US
Cheng-Gang Kong - Saratoga CA, US
Hui-Yin Seto - San Jose CA, US
Andrej Zolotykih - Fryazino, RU
Ivan Pavisic - San Jose CA, US
Sandeep Bhutani - Pleasanton CA, US
Aiguo Lu - Pleasanton CA, US
Ilya Lyalin - Moscow, RU

LSI Corporation - Milpitas CA

G06F 17/50

716114, 716106, 716107, 716108, 716110, 716111, 716112, 716113, 716132, 716134, 703 13, 703 14

A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

20040260962, Dec 23, 2004

Jun 23, 2003

10/601441

Victor Suen - Fremont CA, US
William Lau - Foster City CA, US
Hui-Yin Seto - San Jose CA, US

G06F001/12

713/401000

Systems and methods are provided for latching a data signal. In one embodiment, a system comprises a first delay circuit that programmably delays a strobe signal with a first delay to latch a data signal. The system also comprises a second delay circuit that receives the data signal and delays the data signal with a second delay that is substantially inherent to the first delay. The system may include a logic circuit coupled between the first and the second delay circuits for latching the data signal in substantial alignment with the strobe signal. In one embodiment, similar delays are used in a master delay circuit, while in another embodiment such delays are used in slave devices connected to a master delay circuit.

59132230, Jun 15, 1999

Jan 25, 1993

8/008206

Douglas Parks Sheppard - Southlake TX
William Lau - Dallas TX

G06F 1208

711118

A four-way cache data memory is provided, having a cache data RAM (30) and a tag RAM (28). The tag RAM (28) is enabled to access one of the tags therein. This tag is compared with the tag portion of the received memory address to determine if a tag is stored therein. If a true comparison results, a HIT is indicated and this is utilized to enable a portion of the cache data RAM (30). The data in the enabled portion is then output on the data bus.