William Landucci Phones & Addresses
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Phoenix, AZ
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2804 Old Estates Ct, San Jose, CA 95135
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Cumberland, KY
Publications
Us Patents
Substrate Pads With Reduced Impedance Mismatch And Methods To Fabricate Substrate Pads
View pageUS Patent:
20030107056, Jun 12, 2003
Filed:
Dec 8, 2001
Appl. No.:
10/013326
Inventors:
William Landucci - San Jose CA, US
Assignee:
NATIONAL SEMICONDUCTOR CORPORATION
International Classification:
H01L027/10
US Classification:
257/211000
Abstract:
To significantly reduce parasitic capacitance of component's landing pad, the present invention forms patterned holes in reference potential layers below the pad, thus effectively increasing the dielectric distance between the pad and the reference potential planes below the pad, raising the characteristic impedance of the pad above that of the trace connected to the pad. A controlled amount of parasitic capacitance is re-introduced to the pad by forming at least one grounded metal plate adjacent to the pad, bringing the characteristic impedance of the pad to substantially match that of the trace. The distance of the metal plates from the pad, and the configuration of the patterned holes are predetermined to substantially match the pad's impedance with that of the trace.