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Wenxian Living Zhu

from San Jose, CA
Age ~60
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Also known as:
Wenxian Te Zhu, Wenxian X Zhu, Wenxian Z Zhu, Wen X Zhu, Wen-Xian Zhu, Wenzian Zhu, Wenxian Li, Wen Zhuj
Related to:
Steve G Cherrier, 67Li ZhuWei Li, 45Eba Li, 77Li Zhu, 36Wen Li, 60Quiong Xiong, 63Xuema Li, 63Wei Li, 47Wen LiFangi I Li, 45Julie Zhu, 36Li Wei
Connected to:
Ailin Zhu, 37Anne Q Zhu, 57Annie L Zhu, 71Athena Zhu, 32Banghe Zhu, 52Beck Zhu, 61Ben S Zhu, 56Bessie Zhu, 37Bijun Zhu, 33Bing Q Zhu, 44

Wenxian Zhu Phones & Addresses

  • San Jose, CA
  • 25207 Bright Hollow Ln, Katy, TX 77494
  • San Antonio, TX
  • 921 Gates St, Palo Alto, CA 94303 (650) 328-1307
  • 1066 Colorado Ave, Palo Alto, CA 94303 (650) 813-1337
  • East Palo Alto, CA
  • Hi Vista, CA
  • Ukiah, CA
  • Santa Clara, CA
  • Newark, CA

Resumes

Resumes

Wenxian Zhu Photo 1

Vice President

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Location:
4468 Piper Dr, San Jose, CA 95129
Industry:
Semiconductors
Work:
Anst
Vice President
Syp Aug 2017 - Mar 2019
Senior Director, Ald Technology
Intermolecular Aug 2011 - Apr 2017
Senior Member of Technical Staff and Senior Manager of Technical Transfer
Applied Materials Oct 2008 - Jul 2011
Gpm and Manager, Solar Technology
Novellus Systems Sep 1, 2000 - Oct 1, 2008
Senior Process Engineer and Key Account Technologist
Education:
University of Idaho 1993 - 1997
Doctorates, Doctor of Philosophy, Metallurgical Engineering University of Science and Technology Beijing 1984 - 1987
Master of Science, Masters, Metallurgical Engineering
Skills:
Thin Films
Semiconductors
Semiconductor Industry
Cvd
R&D
Silicon
Design of Experiments
Jmp
Pvd
Characterization
Solar Energy
Pecvd
Failure Analysis
Materials Science
Metrology
Solar Cells
Process Integration
Research and Development
Physical Vapor Deposition
Plasma Physics
Atomic Layer Deposition
Chemical Vapor Deposition
Photolithography
Ald
Semiconductor Process
Etching
Plasma Enhanced Chemical Vapor Deposition
Languages:
Mandarin
English
Wenxian Zhu Photo 2

Wenxian Zhu

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Wenxian Zhu
Co-Owner, Partner
Zw International
Business Consulting /Whol Casting Parts /Whol Doors and Windows · Lumber, Plywood, Millwork, and Wood Panel Merchant Wholesale
1066 Colorado Pl, Palo Alto, CA 94303
1066 Colorado Ave, Palo Alto, CA 94303
(650) 813-1337

Publications

Us Patents

Low Dielectric Constant Fluorine-Doped Silica Glass Film For Use In Integrated Circuit Chips And Method Of Forming The Same

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US Patent:
6844612, Jan 18, 2005
Filed:
Apr 29, 2003
Appl. No.:
10/426643
Inventors:
Jason Tian - Milpitas CA, US
Wenxian Zhu - Palo Alto CA, US
M. Ziaul Karim - San Jose CA, US
Cong Do - San Jose CA, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 2358
US Classification:
257634, 257635, 257650
Abstract:
A fluorine-doped silica glass (FSG) dielectric layer includes a number of sublayers. Each sublayer is doped with fluorine in such a way that the doping concentration of fluorine in the sublayer decreases as one moves from an interior region of the sublayer towards one or both of the interfaces between the sublayer and adjacent sublayers. This structure reduces the generation of HF when the layer is exposed to moisture and thereby improves the stability and adhesion properties of the layer. The principles of this invention can also be applied to dielectric layers doped with such other dopants as boron, phosphorus or carbon.

Method For Controlling Etch Process Repeatability

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US Patent:
7078312, Jul 18, 2006
Filed:
Sep 2, 2003
Appl. No.:
10/654113
Inventors:
Siswanto Sutanto - San Jose CA, US
Wenxian Zhu - Palo Alto CA, US
Waikit Fung - Cupertino CA, US
Mayasari Lim - Union CIty CA, US
Vishal Gauri - San Jose CA, US
George D. Papasouliotis - Cupertino CA, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/76
US Classification:
438424, 438435, 438443, 438699, 438402, 438778, 438959
Abstract:
Plasma etch processes incorporating etch chemistries which include hydrogen. In particular, high density plasma chemical vapor deposition-etch-deposition processes incorporating etch chemistries which include hydrogen that can effectively fill high aspect ratio (typically at least 3:1, for example 6:1, and up to 10:1 or higher), narrow width (typically sub 0. 13 micron, for example 0. 1 micron or less) gaps while reducing or eliminating chamber loading and redeposition and improving wafer-to-wafer uniformity relative to conventional deposition-etch-deposition processes which do not incorporate hydrogen in their etch chemistries.

Biased Hetch Process In Deposition-Etch-Deposition Gap Fill

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US Patent:
7163896, Jan 16, 2007
Filed:
Dec 10, 2003
Appl. No.:
10/733858
Inventors:
Wenxian Zhu - Palo Alto CA, US
Jengyi Yu - San Jose CA, US
Siswanto Sutanto - San Jose CA, US
Pingsheng Sun - San Jose CA, US
Jeffrey Chih-Hou Lowe - Milpitas CA, US
Waikit Fung - Cupertino CA, US
Tze Wing Poon - Sunnyvale CA, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/311
US Classification:
438694, 257E21218
Abstract:
Biased plasma etch processes incorporating Hetch chemistries. In particular, high density plasma chemical vapor etch-enhanced (deposition-etch-deposition) gap fill processes incorporating etch chemistries which incorporate hydrogen as the etchant that can effectively fill high aspect ratio gaps while reducing or eliminating dielectric contamination by etchant chemical species.

Hydrogen Treatment Enhanced Gap Fill

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US Patent:
7211525, May 1, 2007
Filed:
Mar 16, 2005
Appl. No.:
11/082369
Inventors:
Sunil Shanker - Sunnyvale CA, US
Sean Cox - Sunnyvale CA, US
Chi-I Lang - Sunnyvle CA, US
Judy H. Huang - Los Gatos CA, US
Minh Anh Nguyen - San Jose CA, US
Ken Vo - San Jose CA, US
Wenxian Zhu - Palo Alto CA, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/469
H01L 21/31
US Classification:
438788, 257E21547
Abstract:
Methods of filling gaps on semiconductor substrates with dielectric film are described. The methods reduce or eliminate sidewall deposition and top-hat formation. The methods also reduce or eliminate the need for etch steps during dielectric film deposition. The methods include treating a semiconductor substrate with a hydrogen plasma before depositing dielectric film on the substrate. In some embodiments, the hydrogen treatment is used is conjunction with a high rate deposition process.

Helium-Based Etch Process In Deposition-Etch-Deposition Gap Fill

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US Patent:
7344996, Mar 18, 2008
Filed:
Jun 22, 2005
Appl. No.:
11/159834
Inventors:
Chi-I Lang - Sunnyvale CA, US
Wenxian Zhu - Palo Alto CA, US
Ratsamee Limdulpaiboon - Daly City CA, US
Judy H. Huang - Los Gatos CA, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/302
H01L 21/461
US Classification:
438723, 438424, 427469, 427578, 216 64
Abstract:
Plasma etch processes incorporating helium-based etch chemistries can remove dielectric a semiconductor applications. In particular, high density plasma chemical vapor etch-enhanced (deposition-etch-deposition) gap fill processes incorporating etch chemistries which incorporate helium as the etchant that can effectively fill high aspect ratio gaps while reducing or eliminating dielectric contamination by etchant chemical species.

Halogen-Free Noble Gas Assisted Hplasma Etch Process In Deposition-Etch-Deposition Gap Fill

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US Patent:
7476621, Jan 13, 2009
Filed:
Mar 1, 2006
Appl. No.:
11/366220
Inventors:
Minh Anh Nguyen - San Jose CA, US
Chi-I Lang - Sunnyvale CA, US
Wenxian Zhu - Palo Alto CA, US
Judy H. Huang - Los Gatos CA, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/311
US Classification:
438695, 438694, 257E21218
Abstract:
Plasma etch processes incorporating H/Noble gas etch chemistries. In particular, high density plasma chemical vapor etch-enhanced (deposition-etch-deposition) gap fill processes incorporating etch chemistries which incorporate hydrogen and one or more Noble gases as the etchant that can effectively fill high aspect ratio gaps while reducing or eliminating dielectric contamination by etchant chemical species.

Plasma Torch Preventing Gas Backflows Into The Torch

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US Patent:
6452129, Sep 17, 2002
Filed:
Nov 20, 2000
Appl. No.:
09/717487
Inventors:
Wenxian Zhu - San Jose CA
Richard C. Eschenbach - Ukiah CA
Robin A. Lampson - Ukiah CA
John R. Sparkes - Ukiah CA
Assignee:
Retech Systems LLC - Ukiah CA
International Classification:
B23K 1000
US Classification:
2191215, 219 75, 21912151, 31323151
Abstract:
A plasma arc torch is disclosed which has an elongated electrode with an open front and a nozzle with a plasma discharge opening that is coaxial with the electrode. A mounting arrangement includes a ceramic ring that engages the front end of the electrode and a gas ring which concentrically surrounds the ceramic ring. A forward portion of the gas ring, the forward end of the electrode, and the nozzle define a swirl chamber of the torch, and opposing, spaced-apart concentric cylindrical surfaces of the ceramic ring and the gas ring, respectively, form an annulus which extends rearwardly from the swirl chamber. The ceramic ring closes the aft end of the annulus, and the gas ring houses a plurality of plasma gas injection ports which are located immediately forward of the aft end of the annulus. The entire plasma gas for the torch flows from the injection ports generally tangentially into the annulus to prevent a recirculation of gas into the annulus and to impart rotation to the gas after it leaves the ports and as it propagates towards the swirl chamber. The annulus is sufficiently long so that the injected gas spirals through about 5-20 revolutions before it enters the swirl chamber as a substantially uniform, single mass gas flow.

Low Temperature Deposition Of Silicon Containing Layers In Superconducting Circuits

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US Patent:
20170186935, Jun 29, 2017
Filed:
Dec 29, 2015
Appl. No.:
14/982307
Inventors:
- San Jose CA, US
Frank Greer - Pasadena CA, US
Wenxian Zhu - San Jose CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 39/24
H01L 21/285
Abstract:
Provided are superconducting circuits and, more specifically, methods of forming such circuits. A method may involve forming a silicon-containing low loss dielectric (LLD) layer over a metal electrode such that metal carbides at the interface of the LLD layer and electrode. The LLD layer may be formed using chemical vapor deposition (CVD) at a temperature of less than about 500 C. At such a low temperature, metal silicides may not form even though silicon containing precursors may come in contact with metal of the electrode. Silicon containing precursors having silane molecules in which two silicon atoms bonded to each other (e.g., di-silane and tri-silane) may be used at these low temperatures. The LLD layer may include amorphous silicon, silicon oxide, or silicon nitride, and this layer may directly interface one or more metal electrodes. The thickness of LLD layer may be between about 1,000 Angstroms and 10,000 Angstroms.
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Wenxian Living Zhu from San Jose, CA, age ~60 Get Report