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Wah Kit Loh

from Dallas, TX
Age ~73
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Also known as:
Wah K Loh, Wahkit Loh
Phone and address:
6078 Jereme Trl, Dallas, TX 75252
Related to:
Nina J Whitlock, 74Michelle W Jackson, 47Brian S Loh, 42Marcus M Loh, 67Steven S Loh, 36K Michelle Loh, 74Michelle K Loh, 68
Connected to:
Aaron P Loh, 54Alfred R Loh, 88Angeline F Loh, 53Bee C Loh, 53Bianca Loh, 50Bill Loh, 73Carolyn J Loh, 24Charlie Y Loh, 47Christian S Loh, 61Christopher M Loh, 61

Wah Loh Phones & Addresses

  • 6078 Jereme Trl, Dallas, TX 75252
  • 2113 Prairie Creek Dr, Richardson, TX 75080 (972) 238-0412
  • Sugar Land, TX
  • Colton, TX
  • 2113 W Prairie Creek Dr, Richardson, TX 75080 (214) 335-9162

Work

Company: Texas instruments Oct 1985 Position: Design manager

Education

Degree: Master of Science, Masters School / High School: Rice University 1983 to 1985 Specialities: Electronics Engineering

Skills

Ic • Cmos • Semiconductor Industry • Simulations • Semiconductors • Soc • Embedded Systems • Vlsi • Power Management • Integrated Circuit Design • Silicon • Sram • Product Engineering • Low Power Design • Physical Design • Testing • Electronics • Engineering Management • Dft • Debugging • Microelectronics • Circuit Design • Eda • Failure Analysis • Characterization

Industries

Semiconductors

Resumes

Resumes

Wah Loh Photo 1

Design Manager

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Location:
Richardson, TX
Industry:
Semiconductors
Work:
Texas Instruments
Design Manager
Texas Instruments Oct 1983 - Sep 1985
Design Engineer
Texas Instruments Oct 1980 - Sep 1983
Memory Packaging
Education:
Rice University 1983 - 1985
Master of Science, Masters, Electronics Engineering University of Birmingham 1970 - 1973
Bachelors, Bachelor of Science, Electronics Engineering
Skills:
Ic
Cmos
Semiconductor Industry
Simulations
Semiconductors
Soc
Embedded Systems
Vlsi
Power Management
Integrated Circuit Design
Silicon
Sram
Product Engineering
Low Power Design
Physical Design
Testing
Electronics
Engineering Management
Dft
Debugging
Microelectronics
Circuit Design
Eda
Failure Analysis
Characterization

Publications

Us Patents

Method For Reducing Sram Test Time By Applying Power-Up State Knowledge

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US Patent:
7216272, May 8, 2007
Filed:
Feb 23, 2005
Appl. No.:
11/063922
Inventors:
Wah Kit Loh - Richardson TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 29/00
US Classification:
714721, 714719
Abstract:
Methods (, and ) are disclosed for testing a memory device by tailoring an algorithm () used in the testing based on the preferred or intrinsic data state that is obtained upon power-up of an advanced technology SRAM memory device (). The methods (, and ) take advantage of the observation that such SRAM devices repeatedly power-up in a preferred state. Accordingly, one method comprises powering-up the memory device and reading a preferred power-up data state of each cell of the memory device without memory initialization or writes. The method then captures and stores a data state associated with the preferred power-up data state of each cell and utilizes the stored power-up data state or an inverse of the power-up data state to tailor a test pattern used by the test algorithm.

Method For Determining And Classifying Sram Bit Fail Modes Suitable For Production Test Implementation And Real Time Feedback

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US Patent:
7324391, Jan 29, 2008
Filed:
Apr 6, 2005
Appl. No.:
11/100067
Inventors:
Wah Kit Loh - Richardson TX, US
Md Abul Bashar Khan - Dallas TX, US
Kemal Tamer San - Plano TX, US
Jon Charles Lescrenier - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 7/00
US Classification:
365201, 365154, 365156, 714720
Abstract:
A method () for determining various bit failure modes in a static random access memory device. A hard/soft bit failure test sequence is performed on each cell of the memory device to determine whether the cell exhibits a hard bit failure or a soft bit failure, then a data retention test is performed on the cell having soft bit failure to determine whether the cell exhibits a data retention failure. A write or disturb test sequence is then performed on the cell not having data retention failure, and a read or disturb test sequence is performed on the cell having write or disturb failure. Finally, a disturb test sequence is performed on the cell having read or disturb failure, and then an analysis is performed on the data from the tests to determine whether the cell exhibits one of a write, read, or disturb failure.

Sram Static Noise Margin Test Structure Suitable For On Chip Parametric Measurements

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US Patent:
7385864, Jun 10, 2008
Filed:
Sep 12, 2006
Appl. No.:
11/519312
Inventors:
Wah Kit Loh - Richardson TX, US
Donald James Redwine - Canton TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 7/00
US Classification:
365201, 365154, 365200, 365206
Abstract:
A set of memory cell test structures and a method for assessing of the static noise margin (SNM) of a memory cell or cells, using discrete point measurement structures provided either on-chip or within the scribe lines. A set of memory structures may comprise first and second test structures, individually comprising a memory cell, having one or more left and right half-bit test structures having hard-wired connections between select nodes of each memory cell half-bit and one or more voltage supplies. The half-bits of the first test structure are configured for measuring respective left and right standby SNM values, and the half-bits of the second test structure are configured for measuring respective left and right cell ratio values at respective output nodes of the structures, using applied supply voltages for on-chip assessment of the static noise margin of the memory cells.

Method For Constructing Shmoo Plots For Srams

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US Patent:
7821816, Oct 26, 2010
Filed:
Mar 10, 2009
Appl. No.:
12/401181
Inventors:
Xiaowei Deng - Plano TX, US
Theodore W. Houston - Richardson TX, US
Wah Kit Loh - Richardson TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 11/00
US Classification:
365154, 36518909, 36518914, 365203
Abstract:
A method of preparing Shmoo plots where both the number of failures and also the failure type is specified at each test voltage measurement point. A method that uses the operational SRAM array circuitry to determine the type of failure that may have occurred at each test voltage measurement point.

Method For Memory Cell Characterization Using Universal Structure

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US Patent:
7924640, Apr 12, 2011
Filed:
Nov 27, 2007
Appl. No.:
11/945469
Inventors:
Xiaowei Deng - Plano TX, US
Wah Kit Loh - Richardson TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 29/00
US Classification:
365201, 365154, 365156
Abstract:
A test method includes providing an integrated circuit, where the integrated circuit includes a memory base cell, where the memory base cell includes a first storage node set, a second storage node set, a set of other nodes, and a set of circuit elements each having a plurality of terminals, where the set of other nodes includes a first data node for accessing the first storage node set, a first access control node for controlling the access of the first storage node set, a first supply node for supplying the first storage node set, and a second supply node for supplying the second storage node set, where the first and second supply nodes are of the same sinking or sourcing type. The method further includes conducting a circuit element test on a circuit element in the set of circuit elements, where in the circuit element test the first and second supply nodes are not connected together, each terminal of the circuit element is directly forced with an electrical quantity, and an electrical quantity is directly measured from a terminal of the circuit element. Further, the method includes conducting at least one of a static noise margin test or a full cell test on the memory base cell.

Structure And Methods For Measuring Margins In An Sram Bit

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US Patent:
8139431, Mar 20, 2012
Filed:
Feb 18, 2009
Appl. No.:
12/388439
Inventors:
Xiaowei Deng - Plano TX, US
Theodore W. Houston - Richardson TX, US
Wah Kit Loh - Richardson TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 7/00
US Classification:
365201, 36518909, 36518914
Abstract:
Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, methods for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array architecture and circuit design.

Method And Structure For Sram Vmin/Vmax Measurement

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US Patent:
8174914, May 8, 2012
Filed:
Sep 1, 2009
Appl. No.:
12/584219
Inventors:
Xiaowei Deng - Plano TX, US
Wah Kit Loh - Richardson TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 7/00
US Classification:
365201, 365205
Abstract:
A parametric test circuit is disclosed (FIG. B). The test circuit includes a latch circuit having true and complementary terminals. A first access transistor () has a current path connected between the true terminal and a first access terminal () and has a first control terminal. A second access transistor () has a current path connected between the complementary terminal and a second access terminal () and has a second control terminal connected to the first control terminal. A multiplex circuit () is arranged to apply a first voltage (VDD) to the first power supply terminal in response to a first state of a select signal (SEL) and to apply a second voltage (VDD) to the first power supply terminal in response to a second state of a select signal.

Margin Testing Of Static Random Access Memory Cells

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US Patent:
8228749, Jul 24, 2012
Filed:
Jun 4, 2010
Appl. No.:
12/794139
Inventors:
Xiaowei Deng - Plano TX, US
Wah Kit Loh - Richardson TX, US
Lakshmikantha V. Holla - Bangalore, IN
Parvinder Kumar Rana - Bangalore, IN
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 29/50
G11C 11/40
G11C 7/12
US Classification:
365201, 365154, 365190, 365203
Abstract:
A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float during memory operations. The various tests are performed by precharging the bit lines for a column, then floating the bit lines, and while the bit lines are floating, pulsing the word lines of one or more selected cells to cause the voltage on one of the bit lines to discharge. The discharged bit line voltage is then applied to another cell, which is then read in a normal read operation to determine whether its state changed due to the discharged bit line voltage. The memory can be characterized for cell stability, write margin, and read current margin in this manner; the method can also be adapted into a manufacturing margin screen, or used in failure analysis.
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Wah Kit Loh from Dallas, TX, age ~73 Get Report