Search

Vivek M Thirtha

from Portland, OR
Age ~45
Get Report
Also known as:
Vivek Thirta, Vivek A
Connected to:
James H Thirtle, 108Marcy M Thirtle, 62Sylvia M Thirtle, 64Godwin N Thiruchelvam, 38Kalyani C Thiruchelvam, 49Kannan Thirugnanam, 53Venkatesh R Thirukonda, 50Appan S Thirumaligai, 50Kumar Thirumalaiappan, 50Raja S Thirumannamalai, 48

Vivek Thirtha Phones & Addresses

  • Portland, OR
  • 2585 Overlook Dr, Hillsboro, OR 97124 (503) 533-4913
  • Beaverton, OR
  • 100 Maple St, Highland Park, NJ 08904 (732) 745-9937
  • 74 Wyckoff St, New Brunswick, NJ 08901 (732) 745-9937
  • Piscataway, NJ

Work

Company: Intel Jun 2006 Position: Senior process engineer

Education

Degree: PhD School / High School: Rutgers, The State University of New Jersey-New Brunswick 2000 to 2006 Specialities: Materials Science

Skills

Thin Films • Materials Science • Nanotechnology • Semiconductors • Characterization • Design of Experiments • Failure Analysis • Jmp • Cvd

Industries

Semiconductors

Resumes

Resumes

Vivek Thirtha Photo 1

Principal Engineer

View page
Location:
Portland, OR
Industry:
Semiconductors
Work:
Intel since Jun 2006
Senior Process Engineer
rutgers university 2000 - 2006
Graduate student researcher
Education:
Rutgers, The State University of New Jersey-New Brunswick 2000 - 2006
PhD, Materials Science College of Engineering, Pune; University of Pune 1995 - 1999
B.E., Metallurgy
Skills:
Thin Films
Materials Science
Nanotechnology
Semiconductors
Characterization
Design of Experiments
Failure Analysis
Jmp
Cvd

Publications

Us Patents

Gate-All-Around Integrated Circuit Structures Having Fin Stack Isolation

View page
US Patent:
20210305430, Sep 30, 2021
Filed:
Mar 27, 2020
Appl. No.:
16/833208
Inventors:
- Santa Clara CA, US
Stephen SNYDER - Portland OR, US
Biswajeet GUHA - Hillsboro OR, US
William HSU - Hillsboro OR, US
Urusa ALAAN - Hillsboro OR, US
Tahir GHANI - Portland OR, US
Michael K. HARPER - Hillsboro OR, US
Vivek THIRTHA - Portland OR, US
Shu ZHOU - Portland OR, US
Nitesh KUMAR - Beaverton OR, US
International Classification:
H01L 29/78
H01L 29/423
H01L 29/06
H01L 29/165
H01L 29/10
H01L 29/08
H01L 21/02
Abstract:
Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

Depop Using Cyclic Selective Spacer Etch

View page
US Patent:
20200411661, Dec 31, 2020
Filed:
Jun 27, 2019
Appl. No.:
16/454408
Inventors:
- Santa Clara CA, US
Vivek THIRTHA - Portland OR, US
Shu ZHOU - Portland OR, US
Nitesh KUMAR - Beaverton OR, US
Biswajeet GUHA - Hillsboro OR, US
William HSU - Hillsboro OR, US
Dax CRUM - Beaverton OR, US
Oleg GOLONZKA - Beaverton OR, US
Tahir GHANI - Portland OR, US
Christopher KENYON - Portland OR, US
International Classification:
H01L 29/66
H01L 29/06
H01L 21/3105
Abstract:
An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires.
Control profile
Vivek M Thirtha from Portland, OR, age ~45 Get Report