Viorel C Ontalus

7502658, Mar 10, 2009

Feb 19, 2008

12/033502

Steven G. Barbee - Dover Plains NY, US
Jeong W. Nam - Poughquag NY, US
Viorel Ontalus - Danbury CT, US

International Business Machines Corporation - Armonk NY

G06F 19/00

700109, 700 51, 702 82, 702 84

An exemplary method for performing fabrication sequence analysis, the method comprising, defining a process group, wherein a process group includes fabrication processes in a fabrication sequence, determining fabrication process paths in the process group to define independent variables, wherein a process path is a plurality of fabrication equipment used to fabricate a particular semiconductor device in the fabrication sequence, receiving a dependent variable for the fabrication sequence, performing analysis of variance to calculate a p-value for the process group, determining whether the p-value is lower than a threshold value, identifying a poor process path responsive to determining that the p-value is lower than a threshold value, and outputting the identified poor process path.

7687338, Mar 30, 2010

Dec 5, 2007

11/950572

Sameer Jain - Beacon NY, US
Shreesh Narasimha - Beacon NY, US
Karen A. Nummy - Newburgh NY, US
Viorel Ontalus - Danbury CT, US
Jang H. Sim - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY

H01L 21/336

438197, 438220, 438300, 257E2164, 257E21182, 257E21207, 257E21626, 257900

Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET.

7786025, Aug 31, 2010

Mar 17, 2009

12/405702

Oleg Gluschenkov - Tannersville NY, US
Viorel C. Ontalus - Danbury CT, US
Vilmarie Soler - Wallkill NY, US

International Business Machines Corporation - Armonk NY

H01L 21/00

438799, 438305

A method of fabricating an integrated circuit includes providing a gate conductor spaced above a semiconductor substrate by a gate dielectric, a pair of dielectric spacers disposed on sidewall surfaces of the gate conductor, and source and drain regions disposed in the substrate on opposite sides of the dielectric spacers, wherein the gate conductor and the source and drain regions comprise dopants; and subjecting at least a portion of the dopants to at least 3 consecutive anneal exposures to activate the dopants, wherein a duration of each exposure is about 200 microseconds to about 5 milliseconds.

7855110, Dec 21, 2010

Jul 8, 2008

12/169118

Viorel Ontalus - Danbury CT, US
Robert Robison - Colchester VT, US

International Business Machines Corporation - Armonk NY

H01L 21/336

438197, 438305, 438306, 257E21433

An FET and method of fabricating an FET. The method includes forming a gate dielectric layer on a top surface of a silicon region of a substrate and forming a gate electrode on a top surface of the gate dielectric layer; forming a source and a drain in the silicon region and separated by a channel region under the gate electrode, the source having a source extension extending under the gate electrode and the drain having a drain extension extending under the gate electrode, the source, source extension, drain and drain extension doped a first type; and forming a source delta region contained entirely within the source and forming a drain delta region contained entirely within the drain, the delta source region and the delta drain region doped a second dopant type, the second dopant type opposite from the first dopant type.

8035141, Oct 11, 2011

Oct 28, 2009

12/607104

Kevin K. Chan - Yorktown Heights NY, US
Abhishek Dube - Hopewell Junction NY, US
Jinghong Li - Hopewell Junction NY, US
Viorel Ontalus - Hopewell Junction NY, US
Zhengmao Zhu - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY

H01L 29/76

257288, 257213, 257230, 257900, 257902, 257903, 257E2119, 257E2121, 257E21394, 257E21458, 257E21615, 257E21694, 257E21435, 257E21619, 257E29346, 257E29325, 257413, 257255, 257408, 257303

A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.

8236660, Aug 7, 2012

Apr 21, 2010

12/764329

Kevin K. Chan - Staten Island NY, US
Abhishek Dube - Fishkill NY, US
Judson R. Holt - Wappingers Falls NY, US
Jinghong Li - Poughquag NY, US
Joseph S. Newbury - Irvington NY, US
Viorel Ontalus - Danbury CT, US
Zhengmao Zhu - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

H01L 21/336

438301, 438289, 257E21562, 257E21619, 257E21634

Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes at least one monolayer of dopant located within the upper layer of each of the embedded stressor elements.

8278164, Oct 2, 2012

Feb 4, 2010

12/700059

Xi Li - Hopewell Junction NY, US
Viorel C. Ontalus - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY

H01L 21/336

438197, 438 50, 438285, 438300, 438262, 257408, 257E21214, 257E21409, 257E29266

A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.

8338279, Dec 25, 2012

Mar 30, 2011

13/075450

Abhishek Dube - Fishkill NY, US
Viorel Ontalus - Danbury CT, US
Kathryn T. Schonenberg - Wappingers Falls NY, US
Zhengmao Zhu - Poughkeepsie NY, US

International Business Machines Corporation - Armonk NY

H01L 21/20

438492, 438504

A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.