Vernon F Vondeylen

48686905, Sep 19, 1989

Jul 12, 1988

7/218019

Vadim B. Minuhin - Bloomington MN
Vernon F. VonDeylen - Bloomington MN

Magnetic Peripherals Inc. - Minneapolis MN

G11B 509

360 51

A 1,7 decoder is repeatedly initialized during reading of the synchrofield of the record. The decoder includes an oscillator responsive to the record to produce a binary read signal having a frequency f. A first divider produces a source data clock signal having a frequency 2/3 f. A second divider produces a data partition clock signal having a frequency 1/3 f. A phase synchronizer is responsive to the data partition clock signal to synchronize the source data clock signal. An initializer is responsive to the read signal recovered from the preamble of the record to synchronize the data partition clock signal.

48130591, Mar 14, 1989

Apr 15, 1988

7/182264

Vadim B. Minuhin - Bloomington MN
Vernon F. VonDeylen - Bloomington MN

Magnetic Peripherals Inc. - Minneapolis MN

H04B 166

375122

Run length limited codes, such as (1,7) codes are recovered with a dual channel recovery system in which the high resolution channel normally supplies the output (recovered) signal. The low resolution channel includes a detector, such as a delay device and gate, to detect a predetermined absence of transitions in the low resolution signal (which is indicative of long strings of successive zeros) to inhibit the high resolution channel from supplying the output. The result is to effectively block the high resolution channel from providing a false output.

48751081, Oct 17, 1989

Aug 2, 1988

7/227216

Vadim B. Minuhin - Bloomington MN
Evgeny J. Berzon - St. Louis Pk. MN
Vernon F. VonDeylen - Bloomington MN

Magnetic Peripherals Inc. - Minneapolis MN

G11B 509
H03L 700

360 51

A phase lock loop includes a phase shift apparatus to provide a plurality (i. e. , four) phase-shifted clock signals from the VCO. A phase selector is responsive to a triggering signal from a one-shot multivibrator to select the one phase-shifted clock signal next following termination of the trigger signal. The one-shot is responsive to a change between the read and write mode to initiate operation of the phase selector. As a result, the initial phase error between the input signal (read pulses or write clock) and the clock signal of the phase lock loop is no more than 1/8 window.