Resumes
Resumes
Venu Chari Phones & Addresses
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Concord, CA
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Emeryville, CA
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2343 Orchard View Ln, Escondido, CA 92027 (760) 747-7577
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San Francisco, CA
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San Mateo, CA
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San Diego, CA
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Alameda, CA
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2343 Orchard View Ln, Escondido, CA 92027 (760) 960-1623
Work
Position:
Executive, Administrative, and Managerial Occupations
Publications
Us Patents
Data Processing System Having A Star Coupler With Contention Circuitry
View pageUS Patent:
44280467, Jan 24, 1984
Filed:
May 5, 1980
Appl. No.:
6/146805
Inventors:
Venu Chari - San Diego CA
Jack R. Duke - San Marcos CA
Shimon Gersten - San Diego CA
Jack R. Duke - San Marcos CA
Shimon Gersten - San Diego CA
Assignee:
NCR Corporation - Dayton OH
International Classification:
G06F 1516
US Classification:
364200
Abstract:
A data processing system having a plurality of subsystems linked by a star coupler. The star coupler includes contention circuitry for controlling the star coupler so that at any given time no more than one selected subsystem can pass a message through the star coupler. The contention circuitry uses a conventional priority encode circuit to determine the selected one of the subsystems, so that the first message to be received from one of the subsystems is the message passed or, if two or more messages are received from subsystems simultaneously, the message from the subsystem having the highest relative priority established by the priority encode circuit is the message passed. In an embodiment showing an expanded star coupler, the contention circuitry has plural first level contention circuits and a second level contention circuit, each using a conventional priority encode circuit.
Data Communications System To System Adapter
View pageUS Patent:
45625336, Dec 31, 1985
Filed:
Aug 20, 1984
Appl. No.:
6/642736
Inventors:
Alfred Hodel - Au, CH
Dennis B. Merkes - San Diego CA
Venu Chari - San Diego CA
Dennis B. Merkes - San Diego CA
Venu Chari - San Diego CA
Assignee:
NCR Corporation - Dayton OH
International Classification:
G06F 304
US Classification:
364200
Abstract:
This invention relates to an adapter for interprocessor communications and the method therefor. An adapter is included in a data processing system which has a plurality of central systems, each of the plurality of central systems having at least one serial channel control processor. The data processing system further has a dynamic channel exchange for providing switching logic thereby permitting each of the plurality of central systems access to a plurality of peripherals coupled to the dynamic channel exchange. The adapter is operatively connected to the dynamic channel exchange for providing communications between any pair of central systems. The adapter comprises a link control module which provides handshake control to perform message bit/byte synchronization and translation. A message protocol module, which is operatively connected to the link control module, controls the transmission of information with a selected one of the plurality of central systems, the control being administered by interfacing with the serial channel control processor in accordance with a defined message protocol. A data buffer provides intermediate storage of information passed between the pair of central systems.
Data Recovery System For Use With A High Speed Serial Link Between Two Subsystems In A Data Processing System
View pageUS Patent:
42875960, Sep 1, 1981
Filed:
Nov 26, 1979
Appl. No.:
6/098019
Inventors:
Venu Chari - San Diego CA
Assignee:
NCR Corporation - Dayton OH
International Classification:
H04L 2710
US Classification:
375 49
Abstract:
A data recovery circuit for use in a data processing system where plural subsystems are linked by a bit serial transmission line. The data transmitted over the bit serial transmission line is in the form of a phase encoded (PE) pulse signal. The data recovery circuit includes a time delay circuit for delaying the PE pulse signal by a three-quarter bit period. The three-quarter bit period delay signal permits the generation of a control clock signal. The control clock signal is used in sampling the PE pulse signal at three-quarter bit period points in order to generate a control signal that indicates the absence or presence of a transition at the midpoint of each bit period of the PE pulse signal. The control signal is used to generate a recovered clock signal by logically combining the control signal with the PE pulse signal and a one-half bit period delayed PE pulse signal. The control signal is also used to generate a recovered data signal by clocking the control signal into two cascaded flip-flops and logically combining the outputs of the two cascaded flip-flops.
Data Processor Utilizing A Two Level Microaddressing Controller
View pageUS Patent:
41685237, Sep 18, 1979
Filed:
Dec 6, 1977
Appl. No.:
5/858050
Inventors:
Venu Chari - San Diego CA
Ronald L. Engelbrecht - Augusta KS
Ronald L. Engelbrecht - Augusta KS
Assignee:
NCR Corporation - Dayton OH
International Classification:
G06F 920
US Classification:
364200
Abstract:
A data processor utilizes a central processor controller to determine selectively the next required operation phase while executing a current operation phase. Control words contained in a second stage control memory are selectively addressed from addresses contained in a first stage control memory. The selection of a particular address of a control word contained in said first stage control memory is determined from combinations of signals received by a condition multiplexer interposed between said first and second stage control memories, portions of program instructions contained in main memory, externally operated manual switches, and various internal control flags. The operation phase is defined as an operation, which is defined by said control word. The generation of the address for the next required control word and the execution of the operation defined by the current control word occurs in the same machine cycle. Each control word comprises a mode of operation, control signals for the various execute units, and input signals for the condition multiplexer for determining the next operation phase control word address, required by the data processor in the process of executing program instructions contained in the data processor's main memory.