Resumes
Resumes
Design Verification Engineer
View pageLocation:
Milpitas, CA
Industry:
Semiconductors
Work:
Microsoft
Design Verification Engineer
Einfochips Oct 2010 - Oct 2013
Asic - Engineer
Mentor Graphics Oct 2010 - Oct 2013
Senior Application Engineer
Design Verification Engineer
Einfochips Oct 2010 - Oct 2013
Asic - Engineer
Mentor Graphics Oct 2010 - Oct 2013
Senior Application Engineer
Education:
St. Xavier's High School, Loyola Hall
Skills:
Systemverilog
Verilog
Functional Verification
Uvm
Asic
Vmm
Perl
C++
I2C
Communication
Hdmi
Tcl
Debugging
Soc
Vlsi
Respect
Vhdl
Universal Verification Methodology
System on A Chip
Application Specific Integrated Circuits
Verilog
Functional Verification
Uvm
Asic
Vmm
Perl
C++
I2C
Communication
Hdmi
Tcl
Debugging
Soc
Vlsi
Respect
Vhdl
Universal Verification Methodology
System on A Chip
Application Specific Integrated Circuits