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Uday Naik

from Los Altos, CA
Age ~62
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Related to:
Tejas KorwarNikhil Korwar, 37Medha P Korwar, 28Nishad NaikKenneth R Hake, 58Bernie Hake
Connected to:
Abhijeet A Naik, 55Abhijit S Naik, 42Amee P Naik, 47Ameya A Naik, 34Anilkumar R Naik, 57Apoorv Naik, 38Bindi Naik, 46Chaitali D Naik, 28Chinmay Naik, 38Deepali Naik, 43

Uday Naik Phones & Addresses

  • 638 Tomi Lea St, Los Altos, CA 94022
  • 270 Live Oak Ln, Los Altos, CA 94022 (650) 559-0230 (650) 793-7096
  • 21831 Hermosa Ave, Cupertino, CA 95014 (408) 873-8590
  • 11802 Trinity Spring Ct, Cupertino, CA 95014 (408) 873-8590
  • 503 Sylvan Ave, Mountain View, CA 94041 (650) 966-8597
  • San Francisco, CA
  • Santa Clara, CA
  • Milpitas, CA
  • 21831 Hermosa Ave, Cupertino, CA 95014

Work

Position: Professional/Technical

Education

Degree: High school graduate or higher

Resumes

Resumes

Uday Naik Photo 1

Vp, Engineering Fellow

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Location:
1523 Honey Suckle Ct, Pleasanton, CA 94588
Industry:
Computer Software
Work:
Google since Mar 2006
Senior Staff Engineer
Intel 1998 - 2006
Principal engineer
Microware Systems Jun 1992 - Jan 1998
Principal Engineer
Education:
Indiana University Bloomington 1990 - 1992
Master of Science, Computer Science Indian Institute of Technology, Bombay 1986 - 1990
Bachelors, Computer Science
Languages:
English
Uday Naik Photo 2

Principal

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Location:
21194 Lauretta Dr, Cupertino, CA 95014
Industry:
Computer Software
Work:
Opensoft Systems Jun 2005 - Mar 2010
Founder and Chief Technology Officer
Kaiser Permanente Jun 2005 - Mar 2010
Principal
Nextance Apr 2004 - May 2005
Director, Analytics
Tibco Software Inc. Apr 1994 - Sep 2003
Director, Integration Products
Amdahl Hcl-Hp 1991 - 1993
Engineering Positions In R and D
Education:
National Institute of Technology Karnataka
Bachelor of Engineering, Bachelors, Electronics Engineering National Institute of Technology Karnataka
Bachelor of Applied Science, Bachelors, Bachelor of Science
Skills:
Enterprise Architecture
Cloud Computing
Integration
Soa
Distributed Systems
Enterprise Software
Middleware
Product Management
Big Data
Architecture
Software Development
Software Design
Solution Architecture
Saas
Start Ups
Web Services
Java Enterprise Edition
Soap
Software Engineering
E Commerce
Tibco
Architectures
Agile Methodologies
Mobile Devices
Enterprise Integration
Hadoop
Java
Service Oriented Architecture
Mobile Applications
High Performance Computing
Technical Leadership
Rest
Healthcare
Mobile
Emerging Technologies
Engineering Management
Product Strategy
R&D
Eai
Esb
Messaging
Open Source
Mhealth
Bigdata Analytics
Machine Learning
Ibm Infosphere Biginsights
Mobile Computing
Data Science
Big Data Analytics
Deep Learning
Interests:
Science and Technology
Education
Health
Languages:
English
Kannada
Hindi
Certifications:
License Jjjbp5Tv7K5T
License Kbh9Ypvzpvhg
License Rxfczyrknghk
License S66Kkcdt8Br6
Machine Learning: Regression
Machine Learning Foundations: A Case Study Approach
Machine Learning: Classification
Machine Learning: Clustering & Retrieval
Deep Learning Part Ii
Neural Networks and Deep Learning
Improving Deep Neural Networks: Hyperparameter Tuning, Regularization and Optimization
Structuring Machine Learning Projects
Convolutional Neural Networks
Sequences, Time Series and Prediction
Uday Naik Photo 3

Police Constable

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Work:
Géno
Police Constable
Uday Naik Photo 4

Uday Naik

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Uday Naik
President
OPENSOFT SYSTEMS INC
Custom Computer Programing
21831 Hermosa Ave, Cupertino, CA 95014

Publications

Us Patents

Symbolic Buffer Allocation In Local Cache At A Network Processing Element

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US Patent:
7140023, Nov 21, 2006
Filed:
Oct 31, 2003
Appl. No.:
10/699638
Inventors:
Dennis D. Tran - San Jose CA, US
Harshawardhan Vipat - San Jose CA, US
Uday R. Naik - Fremont CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 13/16
US Classification:
718108, 718105, 710 52, 711 5, 711170
Abstract:
According to some embodiments, a portion of local memory allocated to a thread by a programming statement includes an indication of a read/write status of the portion and symbolically references a buffer name wherein the symbolically referenced buffer name includes both letters and numbers.

Network Packet Buffer Allocation Optimization In Memory Bank Systems

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US Patent:
7158438, Jan 2, 2007
Filed:
Mar 29, 2005
Appl. No.:
11/092010
Inventors:
Chen-Chi Kuo - Pleasanton CA, US
Senthil Nathan Arunachalam - Sunnyvale CA, US
Sridhar Lakshmanamurthy - Sunnyvale CA, US
Uday Naik - Fremont CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 8/00
US Classification:
36523003, 710 52, 710 56
Abstract:
An arrangement of buffer in a memory unit including a plurality of memory banks may store information in rows that span the memory banks. Moreover, a processor may be adapted to (i) establish a plurality of buffers to be associated with the memory unit, wherein the size of each buffer is less than the width of a memory bank, and (ii) arrange for a selected buffer to begin in a memory bank other than a memory bank in which a previously selected buffer begins.

Free Packet Buffer Allocation

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US Patent:
7159051, Jan 2, 2007
Filed:
Sep 23, 2003
Appl. No.:
10/668550
Inventors:
Prashant R. Chandra - Sunnyvale CA, US
Uday Naik - Fremont CA, US
Alok Kumar - Santa Clara CA, US
Ameya S. Varde - Santa Clara CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 3/00
US Classification:
710 56, 710 52, 710 57
Abstract:
According to some embodiments, systems an apparatuses may have a communication path to exchange information packets. A processor may process information packets. A buffer pool cache local to the processor may store free buffer handles for information packets when the buffer pool cache local to the processor is not full. A non-local memory may store the free buffer handles for information packets when the buffer pool cache local to the processor is full.

Facilitating Operation Of A Multi-Processor System Via A Resolved Symbolic Constant

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US Patent:
7167908, Jan 23, 2007
Filed:
Sep 27, 2002
Appl. No.:
10/256300
Inventors:
Eswar M. Eduri - Santa Clara CA, US
Uday R. Naik - Fremont CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 15/177
US Classification:
709220
Abstract:
According to some embodiments, operation of a multi-processor system is facilitated via a resolved symbolic constant. For example, configuration information may be determined at a management processor of a multi-processor network router adapted to receive and transmit network packets. A symbolic constant may be resolved at the management processor in a standard program based on the configuration information. It may then be arranged for another processor of the multi-processor network router to execute an executable version of the standard program in accordance with the resolved symbolic constant.

Optimized Back-To-Back Enqueue/Dequeue Via Physical Queue Parallelism

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US Patent:
7336675, Feb 26, 2008
Filed:
Dec 22, 2003
Appl. No.:
10/743392
Inventors:
Uday R. Naik - Fremont CA, US
Prashant R. Chandra - Sunnyvale CA, US
Alok Kumar - Santa Clara CA, US
Ameya S. Varde - Santa Clara CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 12/28
H04L 12/54
US Classification:
370412, 370428
Abstract:
A method and apparatus to receive a plurality of packet from an inflow of a single packet flow. In response to receiving the plurality of packets, a plurality of packet pointers is enqueued into multiple physical queues. Each of the plurality of packet pointers designates one of the plurality of packets from the single packet flow. The plurality of packet pointers are dequeued from the multiple physical queues to transmit the plurality of packets along an outflow of the single packet flow.

Method For Optimizing Queuing Performance

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US Patent:
7433364, Oct 7, 2008
Filed:
Dec 24, 2003
Appl. No.:
10/746273
Inventors:
Prashant R. Chandra - Sunnyvale CA, US
Uday Naik - Fremont CA, US
Alok Kumar - Santa Clara CA, US
Ameya S. Varde - Santa Clara CA, US
David A. Romano - Cumberland RI, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 12/54
US Classification:
370429, 370235, 370412, 370428
Abstract:
Techniques for optimizing queuing performance include passing, from a ring having M slots, one or more enqueue requests and one or more dequeue requests to a queue manager, and determining whether the ring is full, and if the ring is full, sending only an enqueue request to the queue manager when one of the M slots is next available, otherwise, sending both an enqueue request and a dequeue request to the queue manager.

Method And System To Determine Whether A Circular Queue Is Empty Or Full

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US Patent:
7499399, Mar 3, 2009
Filed:
Dec 12, 2003
Appl. No.:
10/735146
Inventors:
Alok Kumar - Santa Clara CA, US
Uday R. Naik - Fremont CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 12/26
US Classification:
370232, 370412, 709213
Abstract:
A method and apparatus to determine whether a circular queue having N slots is empty or fill. A first queue element is dequeued from a current dequeue slot (“CDS”) of the N slots designated by a CDS pointer. The CDS pointer is incremented to designate a new CDS. It is determined whether the circular queue is empty after the incrementing via executing a check comparing relative positions within the circular queue designated by the CDS pointer and a last enqueue slot (“LES”) pointer. It is determined whether the circular queue is full after setting the LES pointer to designate a new enqueue slot of the circular queue into which a second queue element may be enqueued via re-executing the check.

Method And Apparatus To Support A Large Internet Protocol Forwarding Information Base

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US Patent:
7515588, Apr 7, 2009
Filed:
Mar 18, 2004
Appl. No.:
10/804485
Inventors:
Uday R. Naik - Fremont CA, US
Alok Kumar - Santa Clara CA, US
Eswar Eduri - Santa Clara CA, US
Donald F. Hooper - Shrewsbury MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 12/28
H04L 12/56
G06F 7/00
US Classification:
370392, 37039532, 707101
Abstract:
Method and apparatus to support a large Internet Protocol Forwarding Information Base. A packet is received at a network device, the packet including a destination address. A table is indexed into using a portion of the destination address to locate an entry in the table associated with the portion of the destination address. A pool index is derived from the portion of the destination address and is used to identify a pool of data blocks from among a plurality of pools of data blocks. The entry and the pool of data blocks are navigated to find a next-hop for the packet.
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Uday Naik from Los Altos, CA, age ~62 Get Report