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Troy Beukema Phones & Addresses

  • 169 Holbrook Rd, Briarcliff, NY 10510 (914) 941-1222
  • Briarcliff Manor, NY
  • Spring Lake, MI
  • Peekskill, NY
  • Cortlandt Manor, NY
  • Lake Peekskill, NY
  • Elizabethport, NJ
  • Hoffman Estates, IL

Publications

Us Patents

Apparatus And Method For Hardware Implementation Of A Digital Phase Shifter

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US Patent:
6393083, May 21, 2002
Filed:
Jul 31, 1998
Appl. No.:
09/126990
Inventors:
Troy J. Beukema - Peekskill NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04L 2500
US Classification:
375371, 327234, 327235, 327237
Abstract:
An apparatus and method for an improved hardware implementation of a digital phase shifter which provides a simplified process for phase correction of digital signals and eliminates the use of a lookup ROM and complex digital Multipliers. The digital phase shifter operates by applying a phase correction to complex digital I/Q samples in separate stages, where each stage performs a phase rotation by an amount specified directly by the binary values of an integer input phase. In one aspect, an apparatus for applying a phase shift to a complex digital signal comprises a plurality of phase shift stages each having a phase shift value associated therewith, whereby each of the plurality of phase shift stages selectively applies the corresponding phase shift value to the complex digital signal.

Receiver And Integrated Am-Fm/Iq Demodulators For Gigabit-Rate Data Detection

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US Patent:
7512395, Mar 31, 2009
Filed:
Jan 31, 2006
Appl. No.:
11/345159
Inventors:
Troy J. Beukema - Briarcliff Manor NY, US
Scott K. Reynolds - Amawalk NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04B 1/28
US Classification:
455333, 4551901, 455214, 455336, 33252, 33307
Abstract:
This disclosure addresses providing gigabit-rate data transmission over wireless radio links, using carrier frequencies in the millimeter-wave range (>30 GHz). More specifically, a circuit for detection of amplitude-shift keyed (ASK) or other amplitude modulations (AM) which can be easily incorporated into an integrated circuit receiver system is described, making the receiver capable of supporting both complex IQ modulation schemes and simpler, non-coherent on-off or multiple-level keying signals. Several novel radio architectures are also described which, with the addition of a frequency discriminator network, have the capability of handling frequency shift keyed (FSK) or other frequency modulations (FM), as well as AM and complex IQ modulation schemes.

Quadrature Modulation Circuits And Systems Supporting Multiple Modulation Modes At Gigabit Data Rates

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US Patent:
7733980, Jun 8, 2010
Filed:
Jul 14, 2006
Appl. No.:
11/486539
Inventors:
Troy James Beukema - Briarcliff Manor NY, US
Alberto Valdes Garcia - White Plains NY, US
Scott Kevin Reynolds - Amawalk NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03C 1/52
US Classification:
375300, 375261, 375298, 375302, 375305, 375308, 332146, 332120, 327 29, 327232, 327307, 327437
Abstract:
A quadrature modulation circuit includes a mixer circuit including an integrated sign modulation control circuit and a plurality of mixer ports. The mixer ports include a first input port, a second input port, an output port and a sign modulation control port. The modulation circuit generates a modulated signal by operation of the mixer circuit multiplying a modulating signal applied to the first input port with a carrier signal applied to the second input port to generate a mixed signal output from the output port, and by operation of the integrated sign modulation control circuit controlling polarity switching of a signal at one of the mixer ports in response to a sign modulation control signal input to the sign modulation control port.

Apparatus For Stabilizing Convergence Of An Adaptive Line Equalizer

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US Patent:
8000384, Aug 16, 2011
Filed:
Feb 15, 2008
Appl. No.:
12/032610
Inventors:
Troy James Beukema - Briarcliff Manor NY, US
William Richard Kelly - Verbank NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 5/159
US Classification:
375232
Abstract:
Illustrative embodiments provide a computer implemented method and an apparatus for data decorrelation in a line equalizer adaptive system. The apparatus comprises an input and an output, forming a data path there between, wherein the input capable of receiving data to create received data and the output capable of sending data. The apparatus further comprises an adaptive equalizer capable of equalizing the received data, connected to the data path, and a synchronous decorrelator connected to the data path, in communication with the adaptive equalizer, wherein the synchronous decorrelator evaluates an adapt enable output for each received data input to the adaptive equalizer to determine whether the adaptive equalizer can update settings of the line equalizer adaptive system.

Small-Area Digital To Analog Converter Based On Master-Slave Configuration

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US Patent:
8004441, Aug 23, 2011
Filed:
Mar 18, 2010
Appl. No.:
12/727024
Inventors:
Troy J. Beukema - Yorktown Heights NY, US
Marcel A. Kossel - Rüschlikon, CH
Thomas Toifl - Rüschlikon, CH
Jonas Weiss - Rüschlikon, CH
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03M 1/66
US Classification:
341144, 375242
Abstract:
A digital-to-analog (DAC) converter that includes a plurality of dynamically operated slave digital-to-analog (DAC) converters, each having a switched current mirror and a storage capacitor, and a static master digital-to-analog (DAC) converter in communication with the plurality of dynamically operated slave DAC converters, that distributes a current to at least one of the plurality of slave DAC converters such that voltage across the storage capacitor of the at least one slave DAC converter controls the switch current mirror so that the at least one slave DAC converter outputs currents that are equivalent to digital codes applied to the static master DAC converter. A ring counter is used to periodically refresh the charges on the storage capacitors that are lost by leakage. In addition to the periodic updates, an end user may perform immediate updates of selected slave DACs if necessary, via the ring counter.

Adaptive Clock And Equalization Control Systems And Methods For Data Receivers In Communications Systems

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US Patent:
8135100, Mar 13, 2012
Filed:
Aug 20, 2008
Appl. No.:
12/194571
Inventors:
Troy James Beukema - Briarcliff Manor NY, US
William Richard Kelly - Verbank NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04B 1/10
US Classification:
375350, 375233, 375355, 375357
Abstract:
Systems and methods for adaptive clock and equalization control are provided for data receivers, which are based on a “closed loop” sampling clock framework that employs controllable and dynamically adapted time offsets on both local data and amplitude clocks. The controllable clock offsets are dynamically adapted using signal processing methods adapted to achieve optimum sampling of data and amplitude sampling clock signals to accurately detect data bits and optimize system equalization settings, including, decision-feedback equalizer and/or an optional linear equalizer preceding a decision-feedback equalizer.

Dynamic Quadrature Clock Correction For A Phase Rotator System

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US Patent:
8139700, Mar 20, 2012
Filed:
Jun 26, 2009
Appl. No.:
12/492419
Inventors:
Troy J. Beukema - Yorktown Heights NY, US
Steven M. Clements - Research Triangle Park NC, US
Chun-Ming Hsu - Hopewell Junction NY, US
William R. Kelly - Hopewell Junction NY, US
Elizabeth M. May - Research Triangle Park NC, US
Sergey V. Rylov - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04L 25/00
US Classification:
375371, 375376, 327147, 327153
Abstract:
A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.

Receiver And Integrated Am-Fm/Iq Demodulators For Gigabit-Rate Data Detection

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US Patent:
8249542, Aug 21, 2012
Filed:
Jul 22, 2008
Appl. No.:
12/177252
Inventors:
Troy J. Beukema - Briarcliff Manor NY, US
Scott K. Reynolds - Amawalk NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04B 1/28
US Classification:
455333, 4551901, 455214, 455336, 333252, 333307
Abstract:
This disclosure addresses providing gigabit-rate data transmission over wireless radio links, using carrier frequencies in the millimeter-wave range (>30 GHz). More specifically, a circuit for detection of amplitude-shift keyed (ASK) or other amplitude modulations (AM) which can be easily incorporated into an integrated circuit receiver system is described, making the receiver capable of supporting both complex IQ modulation schemes and simpler, non-coherent on-off or multiple-level keying signals. Several novel radio architectures are also described which, with the addition of a frequency discriminator network, have the capability of handling frequency shift keyed (FSK) or other frequency modulations (FM), as well as AM and complex IQ modulation schemes. These radio architectures support this wide variety of modulations by efficiently sharing detector hardware components. The architecture for supporting both quadrature down-conversion and ASK/AM is described first, followed by the ASK/AM detector circuit details, then the AM-FM detector architecture, and finally the most general AM-FM/IQ demodulator system concept and the FSK/FM detector circuit details.
Troy J Beukema from Briarcliff Manor, NY, age ~62 Get Report