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Toshiaki Kirihata Phones & Addresses

  • 10 Misty Ridge Cir, Poughkeepsie, NY 12603 (845) 462-2782
  • Wappingers Falls, NY
  • South Burlington, VT
  • 10 Misty Ridge Cir, Poughkeepsie, NY 12603 (718) 583-5083

Work

Company: Ibm Position: Senior technical staff member

Education

School / High School: Ithaca College

Industries

Information Technology And Services

Resumes

Resumes

Toshiaki Kirihata Photo 1

Embedded Memory Design Manager

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Location:
New York, NY
Industry:
Information Technology And Services
Work:
IBM
Senior Technical Staff Member
Education:
Ithaca College

Publications

Us Patents

Method And Apparatus For The Replacement Of Non-Operational Metal Lines In Drams

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US Patent:
6335652, Jan 1, 2002
Filed:
Jan 18, 2001
Appl. No.:
09/764816
Inventors:
Gerhard Mueller - Wappingers Falls NY
Toshiaki Kirihata - Poughkeepsie NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G05F 1116
US Classification:
327526, 365200
Abstract:
A semiconductor integrated circuit device including a redundant metal line for replacing a non-operational metal line for connecting to a circuit block. The invention further includes a method for decoupling a defective or otherwise non-operational conductive data line from a circuit block to which it is connected, and replacing the defective conductive data line with a redundant line by coupling it to the same circuit block. A spare conductive block is not needed. The redundant metal lines may be used in multiple levels of hierarchy within an integrated circuit device.

System For High-Speed Data Transfer Using A Sequence Of Overlapped Global Pointer Signals For Generating Corresponding Sequence Of Non-Overlapped Local Pointer Signals

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US Patent:
6338103, Jan 8, 2002
Filed:
Mar 24, 1999
Appl. No.:
09/275567
Inventors:
Toshiaki Kirihata - Poughkeepsie NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1328
US Classification:
710 35, 710 33, 713500
Abstract:
A circuit architecture and methodology for providing burst data transfer in high-speed digital circuit applications implements a sequence of overlapped global-pointer signals for generating corresponding sequence of non-overlapped local-pointer signals. One of the global pointer signals starts to be activated per cycle and the pulse width of each global pointer signal is greater than the burst cycle time. A global pointer signal i of a sequence (where i is one of the integers 1:n ) is used to generate a corresponding local pointer signal i that is reset by detecting a time at which the global pointer signal i+1 starts to be activated. This allows for generation of reliable non-overlapped local pointer signals, while using overlapped global pointer signals. Each local generated pointer signal is used to accomplish a respective data transfer, e. g. , from an individual latch to a single data line.

Semiconductor Memory Having Asymmetric Column Addressing And Twisted Read Write Drive (Rwd) Line Architecture

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US Patent:
6370055, Apr 9, 2002
Filed:
Feb 28, 2001
Appl. No.:
09/795761
Inventors:
David Hanson - Brewster NY
Gerhard Mueller - Wappingers Falls NY
Toshiaki Kirihata - Poughkeepsie NY
Assignee:
Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY
International Classification:
G11C 506
US Classification:
365 63, 365 69, 36523003, 365214, 365 51
Abstract:
There is provided a semiconductor memory having a plurality of memory units. The memory includes a plurality of read write drive (RWD) lines horizontally and/or vertically twisted such that the RWD lines are shared between the plurality of memory units. A plurality of columns is included in each of the plurality of memory units. Each of the plurality of columns is adapted to access the plurality of RWD lines through asymmetrical addressing.

Wordline Decoder System And Method

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US Patent:
6400639, Jun 4, 2002
Filed:
Nov 14, 2000
Appl. No.:
09/712628
Inventors:
Brian L. Ji - Fishkill NY
Toshiaki Kirihata - Poughkeepsie NY
Dmitry G. Netis - Brooklyn NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 800
US Classification:
36523006, 36523003, 365 51
Abstract:
A memory decoder system is disclosed. In an exemplary embodiment of the invention, the system includes a matrix of memory cells, arranged into rows and columns, with a plurality of wordline drivers corresponding to each row in the matrix. A group of wordline driver-decoder blocks each contains a subset of the plurality of wordline drivers therein, with each of the wordline driver-decoder blocks being separated by a row control block. The row control block includes control circuitry for the wordline drivers. For any given wordline driver-decoder block, a first group of wordline drivers contained therein is controlled by a row control block located on one side of the given wordline driver-decoder block, while a second group of wordline drivers contained therein is controlled by a row control block located on an opposite side of the given wordline driver-decoder block.

Fuse Latch Having Multiplexers With Reduced Sizes And Lower Power Consumption

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US Patent:
6404264, Jun 11, 2002
Filed:
Dec 6, 1999
Appl. No.:
09/455118
Inventors:
Gabriel Daniel - Jamaica Estates NY
Toshiaki Kirihata - Poughkeepsie NY
Assignee:
Infineon Technologies North America Corp. - San Jose CA
International Business Machines Corporation - Armonk NY
International Classification:
H03K 1762
US Classification:
327407, 327408
Abstract:
A fuse latch for a memory circuit according to the present invention comprises a plurality of address lines, a control signal line provided from a fuse, a multiplexer for multiplexing the plurality of address lines in response to the control signal wherein the multiplexer has only one type transistors, and a decoder for receiving a multiplexed signal from the multiplexer. Since the multiplexer has a smaller size than that of a conventional CMOS multiplexer, a fuse latch circuit of the present invention has a smaller size than that of a conventional fuse latch. The multiplexer preferably has only NMOS transistors. To overcome a voltage drop due to an NMOS threshold voltage, the present invention uses low-threshold NMOSs and/or boosts the transistors in the multiplexer. Alternatively, the voltage drop is successfully converted into a CMOS level by using a dynamic logic circuit. Further, current consumption of a fuse latch circuit of the present invention is reduced by adopting NMOS transistors to which a lower voltage level may be applied.

Method And Structure For Hiding A Refresh Operation In A Dram Having An Interlocked Pipeline

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US Patent:
6404689, Jun 11, 2002
Filed:
Mar 30, 2001
Appl. No.:
09/822430
Inventors:
Toshiaki Kirihata - Poughkeepsie NY
Sang Hoo Dhong - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 700
US Classification:
365222, 23323008
Abstract:
Hiding a refresh operation in a DRAM or eDRAM is achieved by tailoring an external random access time tRC to slightly extend into the internal random access cycle time. This allows for an additional internal random access cycle time tRC after a plurality of external random access cycles n(tRC ) when enabling the corresponding internal random access operation n(tRC ). The additional core random access cycle time tRC is achieved at every n clock, where n tRC /(tRC -tRC ), or at a time defined by the product of tRC and tRC /(tRC -tRC ). The additional core cycle time tRC is used for refreshing the DRAM By scheduling a refresh-to-refresh period equal to or greater than the phase recovery time, a fully command compatible static random access time can be realized with DRAM cells.

Floating Wordline Using A Dynamic Row Decoder And Bitline Vdd Precharge

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US Patent:
6426914, Jul 30, 2002
Filed:
Apr 20, 2001
Appl. No.:
09/839105
Inventors:
Robert H. Dennard - New Rochelle NY
Louis L. Hsu - Fishkill NY
Toshiaki K. Kirihata - Poughkeepsie NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 800
US Classification:
36523006, 36518906, 365203
Abstract:
A short cycle DRAM use a floating wordline, dynamic row decoder and bitline VDD precharge, which improves the array efficiency of the short cycle DRAM (3-6 ns) without compromising its performance. A small size wordline driver circuit is provided to reduce the row size of the short cycle DRAM without compromising row access timing. A dynamic decoding operation is implemented which intentionally allows some of the deselected wordlines to float during row access. A Vdd bitline precharge/sensing technique avoids a detrimental (or positive) coupling effect to the floating wordlines during row accessing. A Vdd data-line (or DQ) precharge for a read operation, and control of incoming data timing avoids a detrimental (or positive) coupling effect for a write operation.

Hierarchical Row Activation Method For Banking Control In Multi-Bank Dram

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US Patent:
6477630, Nov 5, 2002
Filed:
Feb 24, 1999
Appl. No.:
09/257146
Inventors:
Brian Ji - Fishkill NY
Toshiaki Kirihata - Poughkeepsie NY
Dmitry Netis - Beacon NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
US Classification:
711167, 711 5, 36523003, 36523006, 36523008, 36518905, 713500
Abstract:
A memory structure comprises a plurality of banks (each of the banks including a plurality of blocks) a plurality of timing critical address lines connected to all of the blocks in respective ones of the banks (a number of the critical address lines being equal to a number of the banks), and a plurality of dedicated address lines connected to respective ones of the blocks.
Toshiaki T Kirihata from Poughkeepsie, NY, age ~63 Get Report