Tien-Chun Yang

6486682, Nov 26, 2002

Jul 13, 2001

09/904736

Zhigang Wang - San Jose CA
Nian Yang - San Jose CA
Tien-Chun Yang - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2358

324671, 324769, 324765, 438591, 438216, 438261, 438287, 438782

First and second dielectric constants, e and e respectively, for first and second dielectric materials forming a MOS (metal oxide semiconductor) stack are determined. First and second test MOS stacks having first and second total effective oxide thickness, EOT and EOT , respectively, are formed. The first and second test MOS stacks include first and second interfacial structures comprised of the second dielectric material with first and second thickness, T and T , respectively. In addition, the first and second test MOS stacks include first and second high-K structures comprised of the first dielectric material with first and second thickness, T and T , respectively. The thickness parameters EOT , T , T , EOT , T , and T of the test MOS stacks are measured. The dielectric constants, e and e , are then determined depending on relations between values of EOT , T , and T , and between values of EOT , T , and T.

6593590, Jul 15, 2003

Mar 28, 2002

10/112976

Nian Yang - San Jose CA
Zhigang Wang - San Jose CA
Tien-Chun Yang - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2906

257 48, 438 11, 438 14, 438 15, 438 18

A flash memory microelectronic chip ( ) is formed with at least one integral test structure ( ) for electrical measurement of transistor leakage current from the low voltage peripheral transistors. The invention is a very wide finger-type transistor ( ) with minimum channel length and a width of approximately 150,000 m, equal to the estimated total width of the same type of periphery transistors in the chip circuit. One low voltage NMOS ( ) and one low voltage PMOS finger-type transistor ( ) allow monitoring of the standby current contribution from these two types of periphery transistors. Regular current or voltage tests can be applied to the test structure, thus providing information on the correlation of standby currents with single transistor off-state leakage currents.

6728160, Apr 27, 2004

Sep 12, 2002

10/243433

Tien-Chun Yang - San Jose CA
Kurihara Kazuhiro - Sunnyvale CA

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa-Ken

G11C 800

36523006, 36518905, 36518911

A path gate driver circuit of the present invention includes a shunt stage, a level shifter stage, a pull-up stage, and an output stage. The shunt stage has a control terminal coupled to a supply, and an input terminal coupled to a control signal path. The level shifter stage has a first control terminal coupled to the control signal path, a second control terminal coupled to an output terminal of the shunt stage, a first input terminal coupled to a boost-low supply, and a second input terminal coupled to a boost-high supply. The pull-up stage has a control terminal coupled to an output terminal of the level shifter stage, and an input terminal coupled to the boost-high supply. The output stage has a first control terminal coupled to the output terminal of the shunt stage and an output terminal of the pull-up stage, a second control terminal coupled to the control signal path a first input terminal coupled to the boost-low supply, and a second input terminal coupled to the boost-high supply. A boosted control signal is provided at the output terminal of the output stage in response to the control.

6731130, May 4, 2004

Dec 12, 2001

10/017832

Nian Yang - San Jose CA
Zhigang Wang - San Jose CA
Tien-Chun Yang - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G01R 3126

324766, 324716, 324769, 324 715

A non-destructive and non-intrusive, user friendly, easy to setup and efficient system and method of determining the gate oxide thickness of an operational MOSFET used in real circuit applications is provided. Additionally, the present invention determines the gate oxide thickness when the operational MOSFET is operating in the inversion mode.

6734028, May 11, 2004

Mar 28, 2002

10/113152

Tien-Chun Yang - San Jose CA
Nian Yang - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2166

438 17, 438 18, 257 48, 700110, 700121

A method and apparatus for testing semiconductors comprising shallow trench isolation (STI) edge structures. An edge intensive shallow trench isolation structure ( ) is coupled to a voltage source ( ) and a current versus voltage profile is recorded. A planar structure ( ) on the same wafer is coupled to a voltage source and a current versus voltage profile is recorded. An electrical stress is applied to both structures. Additional current profiles of each structure are obtained after the electrical stress. A comparison of difference current profiles obtained for the two types of structures may indicate the presence and/or the extent of STI corner effects. More specifically, a value for a normalized gate current difference for an STI edge intensive structure ( ) greater than normalized gate current difference of a planar structure ( ) is indicative of an increased rate of electron trapping in STI corners, which may indicate that the STI corners are too thin. In this novel manner, STI corner thickness may be observed in a non-destructive, electrical test process, resulting in higher quality and greater reliability of semiconductors using STI processes.

6734080, May 11, 2004

May 31, 2002

10/159078

Nian Yang - San Jose CA
John Jianshi Wang - San Jose CA
Tien-Chun Yang - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2176

438427, 438400, 438424

A semiconductor isolation material deposition system and method that facilitates convenient and efficient integrated multi-step deposition of isolation regions is presented. In one embodiment of the present invention, an integrated circuit includes densely configured component areas and sparsely configured component areas. An active area in a wafer is created and a shallow trench space is formed. A thin layer of TEOS isolation material layer is deposited on top of the active area and the shallow trench. For example, the layer of thin layer of TEOS isolation material is in a range of 4000 to 5000 angstroms thick over the top of underlying active areas. A reverse mask and pre-planarization etch is performed on the thin layer of TEOS isolation material. The remaining TEOS edge spikes between the densely configured component area and the sparsely configured component area are minimal (e. g. , about 500 angstroms.

6756806, Jun 29, 2004

Mar 28, 2002

10/113017

Nian Yang - San Jose CA
Zhigang Wang - San Jose CA
Tien-Chun Yang - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G01R 3106

324769

A method of determining the location of the breakdown in the gate oxide of a MOSFET is disclosed. Additionally, the method determines the location of the breakdown in a manner that is convenient to use and can be easily employed. The method will determine whether there is a breakdown in the gate oxide. If there is a breakdown, the method will enable determination of the location of the breakdown in the gate oxide.

6759295, Jul 6, 2004

Aug 20, 2002

10/224737

Tien-Chun Yang - San Jose CA
Nian Yang - San Jose CA
Zhigang Wang - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01I 21336

438257, 438 14, 438424

A method of determining the active region width ( ) of an active region ( ) by measuring the respective gate currents (I , I , I ) of respective composite capacitance structures ( â), respectively comprising at least one capacitor element ( â) having respective predetermined widths (W ) for fabricating a flash memory semiconductor device, and a device thereby fabricated. The present method also comprises plotting the respective gate currents (I , I , I ) as a quasi-linear function (IW) of the respective predetermined widths (W ), extrapolating a calibration term (W ) from the quasi-linear function (IW), and subtracting the calibration term (W ) from the respective predetermined widths (W ) to define and constrain the active region width ( ) for facilitating device fabrication.