Search

Thomas A Wassick

from Lagrangeville, NY
Age ~66

Thomas Wassick Phones & Addresses

  • 127 Parliman Rd, Lagrangeville, NY 12540 (845) 226-1084
  • 175 Parliman Rd, Lagrangeville, NY 12540 (845) 226-1084
  • 175B Parliman Rd, Lagrangeville, NY 12540 (845) 226-1084
  • La Grange, NY
  • Wappingers Falls, NY

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Publications

Us Patents

Inherently Robust Repair Process For Thin Film Circuitry Using Uv Laser

View page
US Patent:
6427324, Aug 6, 2002
Filed:
Jul 13, 1998
Appl. No.:
09/114790
Inventors:
Peter A. Franklin - Marlboro NY
Arthur G. Merryman - Hopewell Junction NY
Rajesh S. Patel - Fremont CA
Thomas A. Wassick - Lagrangeville NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01K 310
US Classification:
29852, 29830, 257776
Abstract:
A multilayer thin film structure having defined strap repair lines thereon and a method for repairing interconnections in the multilayer thin film structure (MLTF) and/or making engineering changes (EC) are provided. The method comprises determining interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, defining the top surface metallization including a series of orthogonal X conductor lines and Y conductor lines using photoresist and lithography and additive or phototool to selectively expose the photoresist to define top surface strap connections needed to repair the interconnections and/or make ECs, and forming the top surface metallization.

Thin Film Wiring Scheme Utilizing Inter-Chip Site Surface Wiring

View page
US Patent:
6444919, Sep 3, 2002
Filed:
Jun 7, 1995
Appl. No.:
08/477054
Inventors:
Laertis Economikos - Wappingers Falls NY
Mukta Shaji Farooq - Hopewell Junction NY
Michael Ford McAllister - Clintondale NY
Eric Daniel Perfecto - Poughkeepsie NY
Chandrika Prasad - Wappingers Falls NY
Keshav Prasad - San Jose CA
Madhavan Swaminathan - Marietta GA
Thomas Anthony Wassick - Wappingers Falls NY
George White - Hoffman Estates IL
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 103
US Classification:
174255, 174262, 174261
Abstract:
A thin film wiring scheme on a substrate. The thin film wiring scheme includes a plurality of chip connection pads at each of a first and second chip site on the substrate, a plurality of directional wiring lines interspersed between the chip connection pads at each of the first and second chip sites, at least one of the directional wiring lines being orthogonal to at least one of the other directional wiring lines at each of the first and second chip sites, and a plurality of chip site interconnection lines connecting directional wiring lines at the first chip site with the directional wiring lines at the second chip site.

Process Of Top-Surface-Metallurgy Plate-Up Bonding And Rewiring For Multilayer Devices

View page
US Patent:
6455331, Sep 24, 2002
Filed:
May 29, 2001
Appl. No.:
09/867364
Inventors:
Roy Yu - Poughkeepsie NY
Kamalesh S. Desai - Hopewell Junction NY
Peter A. Franklin - Marlboro NY
Suryanarayana Kaja - Hopewell Junction NY
Kimberley A. Kelly - Poughkeepsie NY
Yeeling L. Lee - Amawalk NY
Arthur G. Merryman - Hopewell Junction NY
Frank R. Morelli - Marlboro NY
Thomas A. Wassick - Lagrangeville NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2100
US Classification:
438 4, 438 15, 438 17, 438115, 438662
Abstract:
A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is rotated during the second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.

Inherently Robust Repair Process For Thin Film Circuitry Using Uv Laser

View page
US Patent:
6541709, Apr 1, 2003
Filed:
Nov 1, 1996
Appl. No.:
08/743405
Inventors:
Peter A. Franklin - Marlboro NY
Arthur G. Merryman - Hopewell Junction NY
Rajesh S. Patel - Fremont CA
Thomas A. Wassick - Lagrangeville NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 103
US Classification:
174255, 174250, 174261, 361777
Abstract:
A multilayer thin film structure having defined strap repair lines thereon and a method for repairing interconnections in the multilayer thin film structure (MLTF) and/or making engineering changes (EC) are provided. The method determines interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, defines the top surface metallization including a series of orthogonal X conductor lines and Y conductor lines using photoresist and lithography and additive or subtractive metallization techniques and then uses a phototool to selectively expose the photoresist to define top surface strap connections needed to repair the interconnections and/or make ECs, and forms the top surface metallization.

Uv-Curable Compositions And Method Of Use Thereof In Microelectronics

View page
US Patent:
6682872, Jan 27, 2004
Filed:
Jan 22, 2002
Appl. No.:
10/056245
Inventors:
Krishna G. Sachdev - Hopewell Junction NY
Michael Berger - New Paltz NY
Rebecca Y. Gorrell - Lagrangeville NY
Gregg B. Monjeau - Wallkill NY
Bernadette H. Perry - Wappingers Falls NY
Thomas A. Wassick - Lagrangeville NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G03C 500
US Classification:
430311, 4302701, 430905, 430913, 4284247, 4284248, 428522
Abstract:
Radiation-curable compositions are provided for use in the fabrication of electronic components as passivation coatings; for defect repair in ceramic and thin film products by micropassivation in high circuit density electronic modules to allow product recovery; as a solder mask in electronic assembly processes; for use as protective coatings on printed circuit board (PCB) circuitry and electronic devices against mechanical damage and corrosion from exposure to the environment. The compositions are solvent-free, radiation-curable, preferably uv-curable, containing a polymer binder, which is a pre-formed thermoplastic or elastomeric polymer/oligomer, a monofunctional and/or bifunctional acrylic monomer, a multifunctional (more than 2 reactive groups) acrylated/methacrylated monomer, and a photoinitiator, where all the constituents are mutually miscible forming a homogeneous viscous blend without the addition of an organic solvent. The compositions may also contain inorganic fillers and/or nanoparticle fillers.

Method Of Selective Plating On A Substrate

View page
US Patent:
6823585, Nov 30, 2004
Filed:
Mar 28, 2003
Appl. No.:
10/249305
Inventors:
Mark J. LaPlante - Montgomery NY
Jon A. Casey - Poughkeepsie NY
Thomas A. Wassick - Lagrangeville NY
David C. Long - Wappingers Falls NY
Krystyna W. Semkow - Poughquag NY
Patrick E. Spencer - Rochester NY
Robert A. Rita - Manlius NY
Richard F. Indyk - Wappingers Falls NY
Kathleen M. Wiley - Wappingers Falls NY
Brian R. Sundlof - Beacon NY
James Balz - Walden NY
Lori A. Maiorino - Wappingers Falls NY
Donald R. Wall - Poughkeepsie NY
Glenn A. Pomerantz - Kerhonkson NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01R 4300
US Classification:
29825, 29830, 29846, 29847, 29848, 29851, 29852, 29855, 29856, 2940209, 2940203, 2940213, 2940218
Abstract:
A method and structure to form surface plating metallization on a substrate. Two layers of tape are applied to the surface of the substrate. A first path is cut through both layers of tape exposing the substrate surface. The first path connects at least one conductive via on the top surface of the substrate. A second path is cut through the second layer of tape exposing the first layer of tape. The second path is routed from the first path to an edge of the substrate A seed layer is deposited over the surface of the second layer of tape thereby creating a seeded plating path in the first path and a sacrificial seeded conduction path in the second path. Connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate creates a plated path on the surface of the substrate. The sacrificial path is removed when the tape is removed.

Electronic Package Repair Process

View page
US Patent:
6916670, Jul 12, 2005
Filed:
Feb 4, 2003
Appl. No.:
10/358431
Inventors:
Jon A. Casey - Poughkeepsie NY, US
James G. Balz - Walden NY, US
Michael Berger - New Paltz NY, US
Jerome Cohen - Poughquag NY, US
Charles Hendricks - Wappingers Falls NY, US
Richard Indyk - Wappingers Falls NY, US
Mark LaPlante - Montgomery NY, US
David C. Long - Wappingers Falls NY, US
Lori A. Maiorino - Wappingers Falls NY, US
Arthur G. Merryman - Hopewell Junction NY, US
Glenn A. Pomerantz - Kerhonkson NY, US
Robert A. Rita - Manlius NY, US
Krystyna W. Semkow - Poughquag NY, US
Patrick E. Spencer - Rochester NY, US
Brian R. Sundlof - Beacon NY, US
Richard P. Surprenant - Poughkeepsie NY, US
Donald R. Wall - Poughkeepsie NY, US
Thomas A. Wassick - Lagrangeville NY, US
Kathleen M. Wiley - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L021/00
US Classification:
438 4
Abstract:
A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.

Silicon Chip Carrier With Through-Vias Using Laser Assisted Chemical Vapor Deposition Of Conductor

View page
US Patent:
7019402, Mar 28, 2006
Filed:
Oct 17, 2003
Appl. No.:
10/686640
Inventors:
Paul Stephen Andry - Mohegan Lake NY, US
Leena Paivikki Buchwalter - Hopewell Junction NY, US
Russell Alan Budd - North Salem NY, US
Thomas Anthony Wassick - Lagrangeville NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 23/48
US Classification:
257763, 438672, 438681, 438628, 438629, 438630, 118722, 257762, 257773
Abstract:
This disclosure teaches a method of filling deep vias or capping deep conducting paste filled vias in silicon or glass substrate using laser assisted chemical vapor deposition of metals. This method uses a continuous wave or pulsed laser to heat the via bottom and the growing metal fill selectively by selecting the laser wavelength such that silicon and/or glass do not absorb the energy of the laser in any appreciable manner to cause deposition in the field. Alternatively holographic mask or an array of micro lenses may be used to focus the laser beams to the vias to fill them with metal. The substrate is moved in a controlled manner in the z-direction away from the laser at about the rate of deposition thus causing the laser heating to be focused on the surface region of the growing metal fill.
Thomas A Wassick from Lagrangeville, NY, age ~66 Get Report