Theodore I Kamins from 4132 Thain Way, Palo Alto, CA 94306, age 83, Phone: (650) 494-9247

Resumes

Consulting Professor At Stanford University, Dept. Of Electrical Engineering

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Location:

San Francisco Bay Area

Industry:

Nanotechnology

Publications

Us Patents

Integrated Circuit Substrate That Accommodates Lattice Mismatch Stress

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US Patent:

6429466, Aug 6, 2002

Filed:

Jan 29, 2001

Appl. No.:

09/774199

Inventors:

Yong Chen - Mountain View CA
Scott W. Corzine - Sunnyvale CA
Theodore I. Kamins - Palo Alto CA
Michael J. Ludowise - San Jose CA
Pierre H. Mertz - Mountain View CA
Shih-Yuan Wang - Palo Alto CA

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

H01L 31072

US Classification:

257183, 257184, 257185, 438309

Abstract:

A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The second material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the first material by the second material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates. In the case of silicon-based substrates, the buried layer is preferably SiO that is sufficiently malleable at the growth temperature to allow the deformation of the isolated substrate layer.

Forming A Single Crystal Semiconductor Film On A Non-Crystalline Surface

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US Patent:

6620710, Sep 16, 2003

Filed:

Sep 18, 2000

Appl. No.:

09/664916

Inventors:

Theodore I. Kamins - Palo Alto CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H01L 2120

US Classification:

438479, 438492, 438497, 438503, 117 43, 117 58, 117 90, 117 94, 117 95, 117106

Abstract:

A method of forming a single crystal semiconductor film on a non-crystalline surface is described. In accordance with this method, a template layer incorporating an ordered array of nucleation sites is deposited on the non-crystalline surface, and the single crystal semiconductor film is formed on the non-crystalline surface from the ordered array of nucleation sites. An integrated circuit incorporating one or more single crystal semiconductor layers formed by this method also is described.

Method Of Fabricating And A Device That Includes Nanosize Pores Having Well Controlled Geometries

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US Patent:

6706204, Mar 16, 2004

Filed:

Dec 19, 2001

Appl. No.:

10/027598

Inventors:

Daniel B. Roitman - Menlo Park CA
Dietrich W. Vook - Menlo Park CA
Theodore I. Kamins - Palo Alto CA

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

H01L 2100

US Classification:

216 33, 216 56, 438733

Abstract:

A method of fabricating nanosized holes with controlled geometries employs tools and methods developed in the microelectronics industry. The method exploits the fact that epitaxially grown film thicknesses can be controlled within a few atomic monolayers and that by using etching techniques, trenches and channels can be created that are only a few nanometers wide. The method involves bonding two shallow channels at an angle such that a nanopore is defined by the intersection. Thus, a nanopore-defining device includes a nanopore with dimensions that are determined by the dimensions and orientations of the intersecting channels, with the dimensions being accurately controlled within a few monolayers.

Formation Of Nanoscale Wires

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US Patent:

6773616, Aug 10, 2004

Filed:

Dec 26, 2001

Appl. No.:

10/033408

Inventors:

Yong Chen - Palo Alto CA
Douglas A. A. Ohlberg - Mountain View CA
Theodore I. Kamins - Palo Alto CA
R. Stanley Williams - Redwood City CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

B44C 122

US Classification:

216 41, 216 66, 216 74, 216 77, 216 78, 216 79, 438689, 438733

Abstract:

Self-organized, or self-assembled, nanowires of a first composition may be used as an etching mask for fabrication of nanowires of a second composition. The method for forming such nanowires comprises: (a) providing an etchable layer of the second composition and having a buried insulating layer beneath a major surface thereof; (b) growing self-assembled nanowires on the surface of the etchable layer; and (c) etching the etchable layer anisotropically down to the insulating layer, using the self-assembled nanowires as a mask. The self-assembled nanowires may be removed or left. In either event, nanowires of the second composition are formed. The method enables the formation of one-dimensional crystalline nanowires with widths and heights at the nanometer scale, and lengths at the micrometer scale, which are aligned along certain crystallographic directions with high crystal quality. Further, the method of the present invention avoids traditional lithography methods, minimizes environmental toxic chemicals usage, simplifies the manufacturing processes, and allows the formation of high-quality one-dimensional nanowires over large areas.

Gated Nanoscale Switch Having Channel Of Molecular Wires

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US Patent:

6791338, Sep 14, 2004

Filed:

Jan 31, 2003

Appl. No.:

10/355748

Inventors:

Alexandre Bratkovski - Mountain View CA
Yong Chen - Palo Alto CA
Theodore I Kamins - Palo Alto CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G01R 2700

US Classification:

324600, 3241581, 257 29, 257 30

Abstract:

A gated nanoscale switch operates as a resonant tunneling device. A conductive channel is formed of a pair of conductive molecular wires and a conductive nanoparticle. Each molecular wire is bound, at one end, to the conductive nanoparticle and, at the opposed end, to one of a pair of electrodes. The structure is located upon a dielectric layer that overlies a conductive substrate. The device may be arranged to operate as a switch with the conductive substrate acting as a gate electrode. Alternatively, the device may be employed to measure the electrical (current versus voltage) characteristics of the molecular wires.

Field Effect Transistor With Gate Layer And Method Of Making Same

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US Patent:

6806141, Oct 19, 2004

Filed:

Oct 30, 2003

Appl. No.:

10/696838

Inventors:

Theodore I. Kamins - Palo Alto CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H01L 21336

US Classification:

438270, 438268, 438197

Abstract:

A field effect transistor having a narrow channel and a method for forming such a device. An upstanding nanopillar is formed from a substrate by directional etching of the substrate preferentially masked by a nanoparticle. A stack of planar layers of material is formed adjacent and around the nanopillar. The bottom layer, adjacent the substantially planar top substrate surface, comprises insulating material. A conductive gate layer overlies the bottom layer while a second insulating layer overlies the gate layer. The pillar material is etched to leave a nanopore into which semiconductor material is deposited, forming an upstanding channel, after insulating material has been deposited on the interior of the nanopore. The source or drain may be a conductive substrate or a doped region of the substrate formed immediately beneath the nanopillar with the other electrode formed by doping the region adjacent the top of the channel.

Field Effect Transistor With Channel Extending Through Layers On A Substrate

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US Patent:

6815750, Nov 9, 2004

Filed:

May 22, 2002

Appl. No.:

10/155416

Inventors:

Theodore I. Kamins - Palo Alto CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H01L 31119

US Classification:

257302, 257412, 257382, 257383, 257334

Abstract:

A field effect transistor (FET) has a channel formed in a pore extending up from a conductive portion of a substrate through a stack of planar layers including a first insulating layer, a gate layer, and a second insulating layer. The pore can be upright or inclined relative to the layers. A nanoparticle used for a mask of a directional etching process ultimately defines the size of the pore and therefore the channel width. The substrate or a doped region of the substrate formed immediately beneath the channel can be a source/drain of the FET with the other drain/source being a doped region adjacent the top of the channel. The gate layer can form the gate or can contact a separate gate inside the pore.