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Teshager T Tesfaye

from Mountain View, CA
Age ~57

Teshager Tesfaye Phones & Addresses

  • 1005 Boranda Ave, Mountain View, CA 94040
  • Mt View, CA
  • Arlington, VA
  • Los Altos, CA
  • 187 Hardwick Rd, Redwood City, CA 94062
  • Woodside, CA
  • 353 Florence St, Sunnyvale, CA 94086
  • Schaumburg, IL
  • Morgan Hill, CA

Work

Position: Professional/Technical

Education

Degree: High school graduate or higher

Business Records

Name / Title
Company / Classification
Phones & Addresses
Teshager Tesfaye
Jotika, LLC
Software & Web Consulting Business · Custom Computer Programming Services, Nsk
187 Hardwick Rd, Redwood City, CA 94062
555 Bryant St, Palo Alto, CA 94301
66 Los Altos Ave, Los Altos, CA 94022
Teshager Tesfaye
President
4AFRI US, INC
PO Box 620145, Redwood City, CA 94062

Publications

Us Patents

Systems And Methods For Preserving The Order Of Data

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US Patent:
7240347, Jul 3, 2007
Filed:
Oct 2, 2001
Appl. No.:
09/967943
Inventors:
Raymond Marcelino Manese Lim - Los Altos Hills CA, US
Stefan Dyckerhoff - Palo Alto CA, US
Jeffrey Glenn Libby - Cupertino CA, US
Teshager Tesfaye - Sunnyvale CA, US
Assignee:
Juniper Networks, Inc. - Sunnyvale CA
International Classification:
G06F 9/46
G06F 9/30
H04L 12/28
US Classification:
718100, 712200, 712201, 370392, 370393, 370394
Abstract:
A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory.

Systems And Methods For Preserving The Order Of Data

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US Patent:
8397233, Mar 12, 2013
Filed:
May 23, 2007
Appl. No.:
11/752620
Inventors:
Raymond Marcelino Manese Lim - Los Altos Hills CA, US
Stefan Dyckerhoff - Palo Alto CA, US
Jeffrey Glenn Libby - Cupertino CA, US
Teshager Tesfaye - Sunnyvale CA, US
Assignee:
Juniper Networks, Inc. - Sunnyvale CA
International Classification:
G06F 9/46
G06F 12/00
G06F 13/00
G06F 9/30
H04L 12/28
US Classification:
718100, 712200, 712201, 710 35, 710240, 370392, 370393
Abstract:
A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory.

Systems And Methods For Preserving The Order Of Data

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US Patent:
20130166856, Jun 27, 2013
Filed:
Feb 22, 2013
Appl. No.:
13/774703
Inventors:
JUNIPER NETWORKS, INC. - Sunnyvale CA, US
Stefan Dyckerhoff - Palo Alto CA, US
Jeffrey Glenn Libby - Cupertino CA, US
Teshager Tesfaye - Sunnyvale CA, US
Assignee:
JUNIPER NETWORKS, INC. - Sunnyvale CA
International Classification:
G06F 12/00
US Classification:
711154
Abstract:
A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory.

Communication Controllers And Methods Therefor

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US Patent:
59700700, Oct 19, 1999
Filed:
Aug 20, 1997
Appl. No.:
8/915286
Inventors:
Kin M. Ho - Fremont CA
David C. Banks - Pleasanton CA
John C. Schell - Sunnyvale CA
Tai Quan - San Jose CA
Teshager Tesfaye - Mountain View CA
Kenneth A. Schmahl - San Jose CA
Matthew J. Tedone - Sunnyvale CA
Drew G. Doblar - San Jose CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
H04J 302
US Classification:
370462
Abstract:
A method, in a host adapter circuit configured for coupling a host electronic device with one of a fiber channel loop and a point-to-point communication channel, for receiving data at the host adapter circuit from one of the fiber channel loop and the point-to-point communication channel. The method includes providing a selectable control signal configured for indicating whether the host adapter circuit is coupled to the fiber channel loop or the point-to-point communication channel. The method further includes providing a front-end receive circuit. The front-end receive circuit is configured for coupling with an input data port. The input data port represents one of the fiber channel loop and the point-to-point communication channel. The method also includes coupling the front-end receive circuit with the selectable control signal. Additionally, the method includes coupling an output of the front-end receive circuit with a decoder of the host adapter circuit, wherein the front-end receive circuit is configured to process, responsive to the selectable control signal, either fiber channel loop data from the fiber channel loop or point-to-point data from the point-to-point communication channel from the input data port to provide parallel data having a predefined size to the decoder circuit.

Fiber Channel Automatic Arbitration And Communication Control

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US Patent:
6038235, Mar 14, 2000
Filed:
Aug 20, 1997
Appl. No.:
8/915135
Inventors:
Kin M. Ho - Fremont CA
David C. Banks - Pleasanton CA
John C. Schell - Sunnyvale CA
Tai Quan - San Jose CA
Teshager Tesfaye - Mountain View CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
H04J 302
US Classification:
370462
Abstract:
A method for automatically arbitrating for mastership of a fiber channel loop in a host adapter circuit configured for coupling a host electronic device with the fiber channel loop. The host adapter circuit has a processor and a loop control circuit different from the processor. The loop control circuit is coupled to a memory of the host adapter circuit. The method includes sending out a host ARBITRATE primitive on the fiber channel loop. The method further includes employing the loop control circuit to monitor received ARBITRATE primitives received at the host adapter circuit from the fiber channel loop. There is also included ascertaining, using the loop control circuit, whether one of the received ARBITRATE primitives represents the host ARBITRATE primitive sent out previously. If the one of the received ARBITRATE primitives represents the host ARBITRATE primitive sent out previously, the method includes placing a target device coupled to the fiber channel loop in an OPENED state for receiving data from the host electronic device.

Systems And Methods For Preserving The Order Of Data

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US Patent:
20160019170, Jan 21, 2016
Filed:
Sep 30, 2015
Appl. No.:
14/870683
Inventors:
- Sunnyvale CA, US
Stefan DYCKERHOFF - Palo Alto CA, US
Jeffrey Glenn LIBBY - Cupertino CA, US
Teshager TESFAYE - Sunnyvale CA, US
International Classification:
G06F 13/16
G06F 9/48
G06F 13/40
Abstract:
A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory.
Teshager T Tesfaye from Mountain View, CA, age ~57 Get Report