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Ted S Rakel

from Fort Collins, CO
Age ~65
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Also known as:
Ted Scott Rakel, Ted H Rakel, Theodore S Rakel, Theodore H Rakel, Ted S Rackel
Phone and address:
4924 Switchgrass Ct, Fort Collins, CO 80525
(970) 229-0826
Related to:
Sheila MeyerRichard Meyer, 40Charles MeyerDonald MeyerJoanna J Woods, 47
Connected to:
Nancy E Rakel, 87Timothy S Rakel, 45Jennifer Rakeman, 53Dane Rakentine, 58Brian R Raker, 40Heidi L Raker, 60Jim Raker, 77Jose M Raker, 49Riley A Raker, 42Shelley C Raker, 74

Ted Rakel Phones & Addresses

  • 4924 Switchgrass Ct, Fort Collins, CO 80525 (970) 229-0826
  • 3021 Lawrence Dr, Edgewood, KY 41017 (859) 341-4634 (859) 344-0752
  • San Jose, CA
  • Campbell, CA
  • Fort Thomas, KY
  • West Chester, OH
  • Indianapolis, IN

Resumes

Resumes

Ted Rakel Photo 1

Software Developer At Miner And Miner Gis Analyst At Telvent Miner & Miner

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Location:
Fort Collins, Colorado Area
Industry:
Computer Software
Experience:
Miner and Miner (Public Company; Computer Software industry): Software Developer,  (-) Telvent Miner & Miner (Public Company; Computer Software industry): GIS analyst,  (2005-Present) Synergetics (Computer Software industry): Software deve...
Ted Rakel Photo 2

Ted Rakel

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Publications

Us Patents

Method For Performing Electrical Rules Checks On Digital Circuits With Mutually Exclusive Signals

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US Patent:
6567956, May 20, 2003
Filed:
May 8, 2000
Appl. No.:
09/566765
Inventors:
Ted Scott Rakel - Fort Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1750
US Classification:
716 4, 716 5
Abstract:
A method for reducing false electrical rule violations during the analysis of a digital circuit having mutually exclusive signal relationships therein. The use of designer knowledge about signals which are mutually exclusive in the circuit design is employed to determine, based on all relevant mutually exclusive signal relationships in the circuit design under test, all possible permutations of active signals used in the analysis. For each permutation, the analysis is performed using the active signals associated with the permutation while ignoring the effect of all signals that are inactive based on the mutually exclusive signal relationships. The invention may be applied to any digital circuit test wherein the effect of mutually exclusive signal relationships affects the outcome of the analysis.

Framework For Rules Checking Utilizing Resistor, Nonresistor, Node And Small Node Data Structures

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US Patent:
6523152, Feb 18, 2003
Filed:
Mar 8, 2000
Appl. No.:
09/521866
Inventors:
Ted Scott Rakel - Fort Collins CO
John G McBride - Ft Collins CO
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1750
US Classification:
716 5, 716 4, 716 6
Abstract:
An Electrical Rules Check (ERC) methodology ensures the quality of an electrical circuit through the creation of up to four different data structures, corresponding to one or more nodes, one or more small nodes, one or more non-resistor elements, and one or more resistor elements of the circuit, that are used by an ERC program running on one or more processors. The creation of data structures for small nodes and resistor elements in which less information need be stored for use by the ERC program minimizes the amount of data storage that must be utilized.

Method Of Determining Dc Margin Of A Latch

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US Patent:
6829571, Dec 7, 2004
Filed:
Jun 15, 2000
Appl. No.:
09/595036
Inventors:
Ted Scott Rakel - Fort Collins CO
Douglas S Stirrett - Fort Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1750
US Classification:
703 15, 703 13, 703 14, 716 5, 716 9, 716 2, 714814
Abstract:
DC margin of a latch of a circuit under design is determined by performing three simulations. A simulation is performed to find the trip voltage of the forwarding inverter of the latch. A second simulation is performed to find the one margin of the latch. Lastly, a third simulation is performed to find the zero margin of the latch. During each of the simulations to find the one margin and the zero margin, the worst case input signal path from the various driver circuit elements and signal paths within the circuit under design is determined analytically by accumulating weighted resistance of each of the circuit elements along the signal paths. The weights assigned to the circuit elements are empirically determined based on the topology configuration of each of the circuit elements, e. g. , the type circuit element, the signal being passed through the circuit element and whether a threshold voltage drop occurs between the drive circuit element and the pass circuit element.

Rom-Based Control Unit In A Geometry Accelerator For A Computer Graphics System

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US Patent:
62190717, Apr 17, 2001
Filed:
Oct 6, 1998
Appl. No.:
9/209934
Inventors:
Alan S. Krech - Fort Collins CO
Theodore G. Rossin - Fort Collins CO
Edmundo Rojas - Fort Collins CO
Michael S McGrath - Fort Collins CO
Ted Rakel - Fort Collins CO
Glenn W Strunk - Fort Collins CO
Jon L Ashburn - Fort Collins CO
S Paul Tucker - Ft Collins CO
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1516
US Classification:
345503
Abstract:
The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e. g. , an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc. ) and a plurality of control units (e. g. , a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc. ) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.

System And Method For Calculating Floating Point Exponential Values In A Geometry Accelerator

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US Patent:
59264063, Jul 20, 1999
Filed:
Apr 30, 1997
Appl. No.:
8/847645
Inventors:
S Paul Tucker - Ft Collins CO
Ted Rakel - Fort Collins CO
Assignee:
Hewlett-Packard, Co. - Palo Alto CA
International Classification:
G06F 738
US Classification:
364753
Abstract:
A novel system and method computes a floating point value of an exponential expression in the form of "a. sup. x " in a geometry accelerator. In accordance with one aspect of the invention, the method includes the steps of receiving the values "a" and x of the exponential expression, where both "a" and x are represented in floating point format. As will be appreciated by those skilled in the art, the values will by supplied by software through an appropriate graphics application program interface (API). The method utilizes a mantissa value of the floating point representation of "a" to index a first value in a first look-up table, the value being an approximation for log2(a). Then, the method multiplies the looked-up value by the value of x to obtain an intermediate result. This intermediate result is then partitioned into a fractional component and an integer component, wherein the fractional component is normalized/converted to floating point format. The method then utilizes a mantissa value of the floating point representation of the fractional component of the intermediate result to index a first value in a second look-up table, the value being an approximation for 2. sup.

Centralized Branch Intelligence System And Method For A Geometry Accelerator

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US Patent:
61849022, Feb 6, 2001
Filed:
Apr 30, 1997
Appl. No.:
8/845975
Inventors:
Alan S. Krech - Fort Collins CO
Theodore G. Rossin - Fort Collins CO
Glenn W Strunk - Fort Collins CO
Michael S McGrath - Fort Collins CO
Edmundo Rojas - Fort Collins CO
S Paul Tucker - Fort Collins CO
Jon L Ashburn - Fort Collins CO
Ted Rakel - Fort Collins CO
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1516
US Classification:
345503
Abstract:
The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by providing a branch central intelligence mechanism. Architecturally, the geometry accelerator includes a plurality of processing elements (e. g. , an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc. ) and a plurality of control units (e. g. , a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc. ) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.

Rom-Based Control Units In A Geometry Accelerator For A Computer Graphics System

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US Patent:
59560479, Sep 21, 1999
Filed:
Apr 30, 1997
Appl. No.:
8/846363
Inventors:
Alan S. Krech - Fort Collins CO
Theodore G. Rossin - Fort Collins CO
Edmundo Rojas - Fort Collins CO
Michael S McGrath - Fort Collins CO
Ted Rakel - Fort Collins CO
Glenn W Strunk - Fort Collins CO
Jon L Ashburn - Fort Collins CO
S Paul Tucker - Fort Collins CO
Assignee:
Hewlett-Packard Co. - Palo Alto CA
International Classification:
G06F 1516
US Classification:
345503
Abstract:
The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e. g. , an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc. ) and a plurality of control units (e. g. , a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc. ) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.
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Ted S Rakel from Fort Collins, CO, age ~65 Get Report