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Taras A Kirichenko

from Houston, TX
Age ~48
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Also known as:
Taras A Krichenko, Kirichenko Taras
Phone and address:
2828G W Holcombe Blvd APT G, Houston, TX 77025
(512) 293-3033
Related to:
Galina Kirichenko
Connected to:
Alexander A Kirichenko, 91Alexey V Kirichenko, 40Elena V Kirichenko, 61Maria F Kirichenko, 94Marina Kirichenko, 31Veronika Kirichenko, 31Vladimir A Kirichenko, 35Laurie A Kiricoples, 62Milutin Kiridzic, 72Maria A Kirigin, 32

Taras Kirichenko Phones & Addresses

  • 2828G W Holcombe Blvd APT G, Houston, TX 77025 (512) 293-3033
  • 5106 Lamar Blvd, Austin, TX 78751 (512) 419-7994
  • 6325 Yaupon Dr, Austin, TX 78759 (512) 372-9901
  • 5106 N Lamar Blvd APT 165, Austin, TX 78751 (512) 769-9119

Work

Company: Velocity merchant energy, lp Jul 1, 2014 Position: Quant trader

Education

Degree: Doctorates, Doctor of Philosophy School / High School: The University of Texas at Austin 1998 to 2004 Specialities: Electrical Engineering

Skills

Monte Carlo Simulation • Derivatives • Quantitative Finance • Commodity Markets • Valuation • Simulations • Mathematical Modeling • Quantitative Analytics • Physics • Modeling • C++ • Financial Risk • Matlab • Vba • Unix • Data Mining • Predictive Analytics

Languages

Russian • Ukrainian

Industries

Financial Services

Resumes

Resumes

Taras Kirichenko Photo 1

Quant Trader

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Location:
P/O Box 11628, Aspen, CO
Industry:
Financial Services
Work:
Velocity Merchant Energy, Lp
Quant Trader
Citi Jul 2010 - Apr 2014
Quantitative Analyst
Freescale Semiconductor Dec 2004 - Jun 2010
Engineer
The University of Texas at Austin Sep 1998 - May 2005
Graduate Research Assistant
Education:
The University of Texas at Austin 1998 - 2004
Doctorates, Doctor of Philosophy, Electrical Engineering Moscow Institute of Physics and Technology (State University) (Mipt) 1994 - 1998
Bachelors, Bachelor of Science, Mathematics, Physics
Skills:
Monte Carlo Simulation
Derivatives
Quantitative Finance
Commodity Markets
Valuation
Simulations
Mathematical Modeling
Quantitative Analytics
Physics
Modeling
C++
Financial Risk
Matlab
Vba
Unix
Data Mining
Predictive Analytics
Languages:
Russian
Ukrainian

Publications

Us Patents

Stressed Semiconductor Device And Method For Making

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US Patent:
7821055, Oct 26, 2010
Filed:
Mar 31, 2009
Appl. No.:
12/414763
Inventors:
Konstantin V. Loiko - Austin TX, US
Cheong M. Hong - Austin TX, US
Taras A. Kirichenko - Austin TX, US
Brian A. Winstead - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 29/788
H01L 29/792
US Classification:
257316, 257325, 257326, 257E293, 257E21179, 438267, 438283, 438287
Abstract:
A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion. A storage layer is formed over the select gate portion and over the first portion of the semiconductor layer. A second layer of gate material is formed over the storage layer. The second layer of gate material is etched to remove a first portion of the second layer of gate material over a first portion of the select gate portion. A portion of the first portion of the select gate is etched out to leave an L-shaped select structure. The result is a memory cell with an L-shaped select gate.

Method For Making A Stressed Non-Volatile Memory Device

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US Patent:
7960267, Jun 14, 2011
Filed:
Mar 31, 2009
Appl. No.:
12/414778
Inventors:
Konstantin V. Loiko - Austin TX, US
Brian A. Winstead - Austin TX, US
Taras A. Kirichenko - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/3205
H01L 21/4763
US Classification:
438591, 438593, 438594, 257E21092, 257E21209
Abstract:
A method of making a semiconductor device on a semiconductor layer includes: forming a gate dielectric over the semiconductor layer; forming a layer of gate material over the gate dielectric; etching the layer of gate material to form a select gate; forming a storage layer that extends over the select gate and over a portion of the semiconductor layer; depositing an amorphous silicon layer over the storage layer; etching the amorphous silicon layer to form a control gate; and annealing the semiconductor device to crystallize the amorphous silicon layer.

Split-Gate Thin Film Storage Nvm Cell With Reduced Load-Up/Trap-Up Effects

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US Patent:
20080188052, Aug 7, 2008
Filed:
Feb 6, 2007
Appl. No.:
11/671809
Inventors:
Brian A. Winstead - Austin TX, US
Taras A. Kirichenko - Austin TX, US
Konstantin V. Loiko - Austin TX, US
Ramachandran Muralidhar - Austin TX, US
Rajesh A. Rao - Austin TX, US
Ko-Min Chang - Austin TX, US
Jane Yater - Austin TX, US
International Classification:
H01L 21/336
US Classification:
438299
Abstract:
A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device () by forming a select gate structure () on a first dielectric layer () over a substrate (); forming a control gate structure () on a second dielectric layer () having embedded nanocrystals () so that the control gate () is adjacent to the select gate structure () but separated therefrom by a gap (); forming a floating doped region () in the substrate () below the gap () formed between the select gate structure and control gate structure; and forming source/drain regions () in the substrate to define a channel region that includes the floating doped region ().
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Taras A Kirichenko from Houston, TX, age ~48 Get Report