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Takumi Yanagawa

from Fremont, CA
Age ~55
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Also known as:
Toshiko Yanagawa, Takami Yanagawa
Phone and address:
48175 Leigh St, Fremont, CA 94539
(510) 573-2741
Related to:
Toshiko Yanagawa, 55Emi YanagawaReiko Yanagawa
Connected to:
Brian W Yanagi, 29Thomas H Yanagi, 57Rodney R Yanagida, 66Ann M Yanagihara, 69Kazuhisa Yanagihara, 59Mikio Yanagisawa, 39Noriko Yanagisawa, 47Osamu Yanagisawa, 53Midori Yanagita, 67Walter S Yanagita, 80

Takumi Yanagawa Phones & Addresses

  • 48175 Leigh St, Fremont, CA 94539 (510) 573-2741
  • 4400 Cushing Pkwy, Fremont, CA 94538
  • Hayward, CA
  • Alameda, CA
  • 48175 Leigh St, Fremont, CA 94539

Work

Position: Installation, Maintenance, and Repair Occupations

Resumes

Resumes

Takumi Yanagawa Photo 1

Technical Director Senior

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Lam Research
Technical Director Senior
Applied Materials Jan 2016 - Apr 2017
Process Engineer Director and Senior Direcor
Applied Materials Jun 1, 2014 - Dec 2015
Process Engineer Director
Lam Research Oct 2006 - May 2014
Senior Engineering Manager and Technical Director
Lam Research Aug 2000 - Oct 2006
Process Engineer and Senior and Staff
Education:
Yokohama National University 1994 - 1996
Master of Science, Masters, Physics
Skills:
Thin Films
Semiconductors
Engineering Management
Plasma Etch
Design of Experiments
Silicon
Metrology
Cvd
Atomic Layer Deposition
Semiconductor Industry
Failure Analysis
R&D
Spc
Ic
Electronics
Takumi Yanagawa Photo 2

Takumi Yanagawa

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Publications

Us Patents

Method For Plasma Etching Performance Enhancement

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US Patent:
20070026677, Feb 1, 2007
Filed:
Aug 22, 2006
Appl. No.:
11/508725
Inventors:
Bing Ji - Pleasanton CA, US
Erik Edelberg - Castro Valley CA, US
Takumi Yanagawa - Fremont CA, US
Zhisong Huang - Fremont CA, US
Lumin Li - Santa Clara CA, US
International Classification:
H01L 21/302
US Classification:
438689000, 156345240
Abstract:
A method for etching features in a dielectric layer is provided. A mask is formed over the dielectric layer. A protective silicon-containing coating is formed on exposed surfaces of the mask. The features are etched through the mask and protective silicon-containing coating. The features may be partially etched before the protective silicon-containing coating is formed.

Reducing Twisting In Ultra-High Aspect Ratio Dielectric Etch

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US Patent:
20080119055, May 22, 2008
Filed:
Nov 21, 2006
Appl. No.:
11/562335
Inventors:
Bing Ji - Pleasanton CA, US
Erik A. Edelberg - Castro Valley CA, US
Takumi Yanagawa - Fremont CA, US
International Classification:
H01L 21/306
US Classification:
438710, 15634548, 15634526, 257E21215
Abstract:
An apparatus for etching a dielectric layer contained by a substrate is provided. An etch reactor comprises a top electrode and a bottom electrode. An etch gas source supplies an etch gas into the etch reactor. A first Radio Frequency (RF) source generates a first RF power with a first frequency and supplies the first RF power into the etch reactor, whereas the first frequency is between 100 kilo Hertz (kHz) and 600 kHz. A second RF source generates a second RF power with a second frequency and supplies the second RF power into the etch reactor, whereas the second frequency is at least 10 mega Hertz (MHz).

Reducing Twisting In Ultra-High Aspect Ratio Dielectric Etch

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US Patent:
20110021030, Jan 27, 2011
Filed:
Oct 7, 2010
Appl. No.:
12/900351
Inventors:
Bing Ji - Pleasanton CA, US
Erik A. Edelberg - San Ramon CA, US
Takumi Yanagawa - Fremont CA, US
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
H01L 21/3065
US Classification:
438714, 257E21218
Abstract:
An apparatus for etching a dielectric layer contained by a substrate is provided. An etch reactor comprises a top electrode and a bottom electrode. An etch gas source supplies an etch gas into the etch reactor. A first Radio Frequency (RF) source generates a first RF power with a first frequency and supplies the first RF power into the etch reactor, whereas the first frequency is between 100 kilo Hertz (kHz) and 600 kHz. A second RF source generates a second RF power with a second frequency and supplies the second RF power into the etch reactor, whereas the second frequency is at least 10 mega Hertz (MHz).

Tunability Of Edge Plasma Density For Tilt Control

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US Patent:
20230063007, Mar 2, 2023
Filed:
Feb 2, 2021
Appl. No.:
17/797669
Inventors:
- Fremont CA, US
Stephan K. Piotrowski - San Jose CA, US
Jaewon Kim - Fremont CA, US
Pratik Mankidy - Fremont CA, US
Takumi Yanagawa - Fremont CA, US
Dongjun Wu - San Jose CA, US
Anthony De La Llera - Fremont CA, US
Zehua Jin - Houston TX, US
International Classification:
H01J 37/32
Abstract:
A plasma lining structure is used in a process chamber to block direct line-of-sight for plasma generated within to grounded surface. The plasma lining structure includes a plurality of sections to cover at least one or more portions of an inside surface of a plasma confinement structure disposed in the process chamber. The sections of the plasma lining structure are positioned between a plasma region and the sidewall of the plasma confinement structure, when the plasma lining structure and the plasma confinement structure are disposed in the plasma chamber, such that the sections directly face the plasma region.

Method For Etching An Etch Layer

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US Patent:
20210335624, Oct 28, 2021
Filed:
Oct 29, 2019
Appl. No.:
17/289603
Inventors:
- Fremont CA, US
Takumi YANAGAWA - Fremont CA, US
International Classification:
H01L 21/311
H01J 37/32
C23C 16/455
C23C 16/56
Abstract:
A method of etching features in a stack comprising a dielectric material on a substrate is provided. In a step (a) an etch plasma is generated from an etch gas, exposing the stack to the etch plasma, and partially etching features in the stack. In a step (b) after step (a) an atomic layer deposition process is provided to deposit a protective film on sidewalls. The atomic layer deposition process comprises a plurality of cycles, wherein each cycle comprises exposing the stack to a first reactant gas comprising WF6, wherein the first reactant gas is adsorbed onto the stack and exposing the stack to a plasma formed from a second reactant gas, wherein the plasma formed from the second reactant gas reacts with the adsorbed first reactant gas to form the protective film over the stack. In a step (c) steps (a)-(b) are repeated at least one time.

Reduction Of Sidewall Notching For High Aspect Ratio 3D Nand Etch

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US Patent:
20200126804, Apr 23, 2020
Filed:
Oct 19, 2018
Appl. No.:
16/165471
Inventors:
- Fremont CA, US
Takumi Yanagawa - Fremont CA, US
Anqi Song - Fremont CA, US
International Classification:
H01L 21/311
H01L 21/3213
H01L 21/02
H01L 21/67
Abstract:
Methods and apparatus for etching a high aspect ratio feature in a stack on a substrate are provided. The feature may be formed in the process of forming a 3D NAND device. Typically, the stack includes alternating layers of material such as silicon oxide and silicon nitride or silicon oxide and polysilicon. WFis provided in the etch chemistry, which substantially reduces or eliminates problematic sidewall notching. Advantageously, this improvement in sidewall notching does not introduce other tradeoffs such as increased bowing, decreased selectivity, increased capping, or decreased etch rate.

Method Of Achieving High Selectivity For High Aspect Ratio Dielectric Etch

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US Patent:
20200090945, Mar 19, 2020
Filed:
Nov 19, 2019
Appl. No.:
16/688639
Inventors:
- Fremont CA, US
Takumi Yanagawa - Fremont CA, US
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
H01L 21/311
H01J 37/32
H01J 37/20
H01L 21/3213
Abstract:
Various embodiments herein relate to methods and apparatus for etching a feature in a substrate. Often, the feature is etched in the context of forming a DRAM device. The feature is etched in dielectric material, which often includes silicon oxide. The feature is etched using chemistry that includes WF. Although WFis commonly used as a deposition gas (e.g., to deposit tungsten-containing film), it can also be used during etching. Advantageously, the inclusion of WFin the etch chemistry can increase the etch rate of the dielectric material, as well as increase the selectivity of the etch. Unexpectedly, these benefits can be realized without any increase in capping.

Method Of Achieving High Selectivity For High Aspect Ratio Dielectric Etch

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US Patent:
20190393047, Dec 26, 2019
Filed:
Jun 26, 2018
Appl. No.:
16/019330
Inventors:
- Fremont CA, US
Takumi Yanagawa - Fremont CA, US
International Classification:
H01L 21/311
H01L 21/3213
H01J 37/20
H01J 37/32
Abstract:
Various embodiments herein relate to methods and apparatus for etching a feature in a substrate. Often, the feature is etched in the context of forming a DRAM device. The feature is etched in dielectric material, which often includes silicon oxide. The feature is etched using chemistry that includes WF. Although WFis commonly used as a deposition gas (e.g., to deposit tungsten-containing film), it can also be used during etching. Advantageously, the inclusion of WFin the etch chemistry can increase the etch rate of the dielectric material, as well as increase the selectivity of the etch. Unexpectedly, these benefits can be realized without any increase in capping.
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Takumi Yanagawa from Fremont, CA, age ~55 Get Report