Sweyyan Y Shei

7117143, Oct 3, 2006

Dec 11, 2003

10/735341

Ming Yang Wang - LaFayette CA, US
Sweyyan Shei - Cupertino CA, US
Vincent Chiu - Fremont CA, US

Fortelink, Inc. - Fremont CA

G06F 9/455

703 25, 716 4, 716 2, 716 5, 716 6, 703 13, 703 23, 713400

Before using a netlist description of an integrated circuit as a basis for programming a circuit emulator, a clock analysis tool analyzes the netlist to identify synchronizing circuits including clocked devices (“clock sinks”) such a flip-flops, registers and latches for synchronizing communication between blocks of logic within the IC. The tool initially classifies the clock signal input to each clock sink according to its clock domain, sub-domain and phase. The tool then classifies each synchronizing circuit according to relationships between the classifications of the clock signals it employs to clock its input and output clock sinks. The tool then determines, based on the classification of each synchronizing circuit, whether the emulator can reliably emulate that synchronizing circuit, or whether the tool should automatically modify the netlist description of the synchronizing circuit so that the emulator can emulate it. The tool also generates a warning when an emulator may not reliably emulate a synchronizing circuit and the tool cannot automatically modify it so that the emulator can reliably emulate it.

7120571, Oct 10, 2006

Dec 11, 2003

10/735342

Sweyyan Shei - Cupertino CA, US
Ming Yang Wang - LaFayette CA, US
Vincent Chiu - Fremont CA, US
Neu Choo Ngui - Fremont CA, US

Fortelink, Inc. - Fremont CA

G06F 9/455
G06F 17/50

703 23, 703 25, 716 16

A resource board for a circuit emulator holds programmable logic devices (PLDs) and other emulation resources such as random access memories (RAMs) and employs both hard-wired and network-based virtual signal paths to flexibly route signals between the emulation resources on the resource board and resources mounted on other resource boards, workstations and other external equipment. The resource board also provides the logic and balanced signal paths needed to deliver clock signals to the PLDs and reduces the number of signals needed to communicate with external test equipment by implementing much of the pattern generation and data acquisition functionality needed to test an emulated circuit.

7703054, Apr 20, 2010

Apr 9, 2007

11/697869

Duan-Ping Chen - San Jose CA, US
Sweyyan Shei - Cupertino CA, US
Hung Chun Chiu - Fremont CA, US
Neu Choo Ngui - San Jose CA, US
Ming Yang Wang - Lafayette CA, US

Springsoft, Inc. - Hsinchu

G06F 17/50

716 4, 716 5, 716 6

A synthesizer processes a register transfer level (RTL) netlist description of a circuit to produce a non-optimized gate level netlist preserving all signals referenced by the RTL netlist. The gate level netlist is then processed to identify the circuit's memory devices and to determine logical relationships between its internal signals (all signals other than circuit and memory device input and output signals) and its other signals (circuit and memory device input and output signals). The synthesizer then again processes the RTL netlist to produce an optimized gate level netlist that preserves the identified memory devices, but which omits reference to some or all of the internal signals. A circuit verification system then processes the optimized gate level netlist to produce waveform data representing time-varying behavior of the other signals of the circuit. The waveform data is then processed to produce additional waveform data representing behavior of the internal signals referenced by the RTL netlist in accordance with the determined logical relationships between the internal signals and the other signals.

7970597, Jun 28, 2011

May 15, 2008

12/120895

Meng-Chyi Lin - Pingjhen, TW
Fei-Sheng Hsu - Hsinchu, TW
Sweyyan Shei - Cupertino CA, US

Springsoft, Inc. - Hsinchu

G06F 9/455

703 23, 714 34

A circuit emulator includes emulation resources programmed to emulate a circuit, a clocking system for clocking logic implemented by the emulation resources, a resource interface circuit, a logic analyzer, and a debugger. The resource interface circuit supplies input signals to the emulation resources, stores data representing behavior of signals generated by the emulation resources produces in response to the input signals and configures operating characteristics of the clocking system. Upon detecting a specified event in the selected signals of the emulation resources, the logic analyzer asserts a trigger signal telling the clocking system to stop clocking the emulation resources. Communicating with the resource interface circuit and the logic analyzer via a packet routing network, the debugger acquires and processes the data stored by the resource interface circuit and transmits commands to the resource interface circuit and the logic analyzer specifying clocking system operating characteristics, controlling signal data transfer to the debugger, and defining the signal events the logic analyzer is to detect.

8255853, Aug 28, 2012

Apr 8, 2010

12/756990

MingYang Wang - Lafayette CA, US
Sweyyan Shei - Cupertino CA, US
Hwa Mao - Taipei, TW

SpringSoft USA, Inc. - San Jose CA
SpringSoft, Inc. - Hsinchu

G06F 17/50

716116, 716117, 716121

An apparatus for circuit emulation may include a first circuit board, one or more circuit emulation resource on the first circuit board, a first interconnection interface on the first circuit board, and a second interconnection interface on the first circuit board. The first circuit board may include conductive wiring paths. The circuit emulation resource is on the first circuit board and coupled with a portion of the conductive wiring paths, with each circuit emulation resource being configured to emulate a portion of an electronic circuit by receiving input signals and producing output signals in response to the input signals. The first interconnection interface is on the first circuit board and coupled with at least a first portion of the circuit emulation resource, The first interconnection interface may be configured to couple with an interconnection interface of a second circuit board having a second group of conductive wiring paths and having a second group of circuit emulation resources. The second interconnection interface is on the first circuit board and coupled with at least a second portion of the at least one circuit emulation resource. The second interconnection interface may be configured to couple with an interconnection interface of a third circuit board having a third group of conductive wiring paths and having a third group of circuit emulation resources.

20040254779, Dec 16, 2004

Jun 16, 2003

10/463057

Ming Wang - LaFayette CA, US
Sweyyan Shei - Cupertino CA, US
Vincent Chiu - Fremont CA, US

G06F009/455

703/027000

An apparatus for emulating the behavior of an electronic device under test (DUT) includes a computer and one or more resource boards containing emulation resources suitable for emulating portions of the DUT. Each resource board includes transaction device for communicating with one another and with the computer network via data packets transmitted over a packet routing network. The packet routing network and the transaction device on each resource board provide “virtual signal paths” between input and output terminals of resources mounted on separate resource boards. To do so, a transaction device on one resource board sends packets containing data indicating output signal states of local emulation resources to a transaction device on another resource board when then drives signals supplied to input terminals of its local emulation resources to the states indicated by the data conveyed in the packet. When the workstation is to emulate a portion of the DUT, the packet routing network also provides virtual signal paths between the workstation and the resource boards. The computer also transmits programming data to the emulation resources via the packet routing network.

20130035925, Feb 7, 2013

Aug 29, 2012

13/597997

Yingtsai Chang - Fremont CA, US
Sweyyan Shei - Cupertino CA, US
Hung Chun Chiu - Fremont CA, US
Hwa Mao - Taipei City, TW
Ming Yang Wang - Lafayette CA, US
Yuchin Hsu - Cupertino CA, US

G06F 9/455

703 28

A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation.

20130055177, Feb 28, 2013

Aug 28, 2012

13/596069

Hung Chun Chiu - Fremont CA, US
Meng-Chyi Lin - Miaoli County, TW
Kuen-Yang Tsai - Hsinchu City, TW
Sweyyan Shei - Cupertino CA, US
Hwa Mao - Taipei, TW
Yingtsai Chang - Fremont CA, US

SPRINGSOFT USA, INC. - San Jose CA
SPRINGSOFT, INC. - Hsinchu City

G06F 17/50

716104

User's RTL design is analyzed and instrumented so that signals of interest are preserved and can be located in the net list after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the net list to ensure that signal values can be accessed at runtime. After that, a P&R process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in FPGAs. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.