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Swapneel A Kekre

from Sunnyvale, CA
Age ~47
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Also known as:
Swapneel Ajit Kekre, Swapneel A Keke
Phone and address:
893 S Knickerbocker Dr, Sunnyvale, CA 94087
Related to:
James H AmolPriti A Kekre, 56
Connected to:
Ashwin Kekre, 42Rahul Kekre, 39Brian Kekua, 41Ashlee Kekuewa, 31Anthony Kekula, 65Jennifer T Kekumu, 41Juan O Kela, 91Asaad N Kelada, 84Melad S Kelada, 59Sherif A Kelada, 46

Swapneel Kekre Phones & Addresses

  • 893 S Knickerbocker Dr, Sunnyvale, CA 94087
  • 710 Navajo Way, Fremont, CA 94539
  • Cupertino, CA
  • Clemson, SC
  • Alameda, CA

Resumes

Resumes

Swapneel Kekre Photo 1

Director R And D

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Location:
San Francisco, CA
Industry:
Computer Software
Work:
HP since Jan 2008
Kernel Design Engineer
Hewlett Packard Co Aug 2001 - Jan 2008
Software Design Engineer
SYSTIME 1998 - 1999
Software Engineer
Education:
Clemson University 1999 - 2001
MS, Computer Science University of Mumbai 1995 - 1998
BE, Computer Engineering
Skills:
Operating Systems
Unix
Software Development
Hp Ux
Storage
Enterprise Software
Testing
Debugging
Software Design
Kernel
Sdlc
Java
Kernel Programming
Management
Performance Tuning
Project Management
Cross Functional Team Leadership
Leadership
People Management
Project Planning
Team Leadership
Coaching
Swapneel Kekre Photo 2

Swapneel Kekre

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Location:
Sunnyvale, CA
Industry:
Computer Software

Publications

Us Patents

Per Processor Set Scheduling

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US Patent:
7793293, Sep 7, 2010
Filed:
Nov 1, 2004
Appl. No.:
10/979060
Inventors:
Scott J. Norton - San Jose CA, US
Hyun J. Kim - Sunnyvale CA, US
Swapneel Kekre - Sunnyvale CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 9/46
US Classification:
718102, 718105
Abstract:
An arrangement, in a computer system, for coordinating scheduling of threads on a plurality of processor sets (PSETs). The arrangement includes a first processor set (PSET) having a first set of scheduling resources, the first set of scheduling resources. The arrangement further includes a second processor set (PSET) having a second set of scheduling resources. The first set of scheduling resources is configured to schedule threads assigned to the first PSET only among processors of the first PSET, and the second set of scheduling resources is configured to schedule threads assigned to the second PSET only among processors of the second PSET.

Thread Hand Off

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US Patent:
8032884, Oct 4, 2011
Filed:
Oct 31, 2006
Appl. No.:
11/555229
Inventors:
Harshadrai Parekh - San Jose CA, US
Colin Edward Honess - San Rafael CA, US
Douglas V. Larson - Santa Clara CA, US
Swapneel Kekre - Sunnyvale CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 9/46
US Classification:
718100, 718102, 718104
Abstract:
Systems, methods, and devices, including computer executable instructions for transferring threads are described. The method comprises determining an idle processor by checking a handoff state of the processor prior to placing an identified runnable thread in a run queue of an idle processor. The method also comprises transferring the runnable thread to a determined idle processor by setting the handoff state of the processor to a handle of the runnable thread.

Asynchronous Wakeup Mechanism That Places Reference To Process On Sleep Queue If Execution Of Copyout Functionality Is Caused To Sleep

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US Patent:
8214834, Jul 3, 2012
Filed:
Apr 30, 2007
Appl. No.:
11/742555
Inventors:
Vasudevan Sangili - San Jose CA, US
Chukwuma Valentine Akpuokwe - Sunnyvale CA, US
Swapneel Kekre - Sunnyvale CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 9/46
US Classification:
718102
Abstract:
A system for asynchronous process sleep or wake management and corresponding methods thereof are described. The system comprises a sleep queue hash table, a process, and a first sleep object and a second sleep object. The first and second sleep objects each comprise a sleep queue and each of the first and second sleep objects are associated with the process. The system further comprises one or more kernel-space processes arranged to perform at least one of associating the first sleep object with the sleep queue hash table and designating the second sleep object to be used for sleeping the process.

Thread Transfer Between Processors

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US Patent:
20060020701, Jan 26, 2006
Filed:
Mar 7, 2005
Appl. No.:
11/074973
Inventors:
Harshadrai Parekh - San Jose CA, US
Swapneel Kekre - Sunnyvale CA, US
International Classification:
G06F 15/173
US Classification:
709226000
Abstract:
Apparatus and methods are provided for transferring threads. One embodiment of a computing device includes a number of processors including a first processor, a memory in communication with the at least one of the number of processors, and computer executable instructions stored in memory and executable on at least one of the number of processors. The computer executable instructions include instructions to select a second processor, wherein the selection is based upon proximity of the second processor to the first processor. Computer executable instructions also include instructions to select a thread for transfer from the second processor and transfer the selected thread from the second processor to the first processor.

Adaptive Cooperative Scheduling

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US Patent:
20060095909, May 4, 2006
Filed:
Nov 1, 2004
Appl. No.:
10/979407
Inventors:
Scott Norton - San Jose CA, US
Hyun Kim - Sunnyvale CA, US
Swapneel Kekre - Sunnyvale CA, US
International Classification:
G06F 9/46
US Classification:
718100000
Abstract:
A method in a computer system for coordinating scheduling of threads among a plurality of processors. The method includes collecting, using a cooperative scheduling component (CSC), system data pertaining to the plurality of processors. The method further includes calculating, using the CSC, unified scheduling-related parameters (USRPs) from the system data. The method additionally includes furnishing the USRPs from the CSC to at least two of a thread launcher, a thread balancer, and a thread stealer, whereby at least two of the thread launcher, the thread balancer, and the thread stealer employ the USRPs to perform their respective scheduling-related tasks.

Automatic Policy Selection

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US Patent:
20060168254, Jul 27, 2006
Filed:
Nov 1, 2004
Appl. No.:
10/979412
Inventors:
Scott Norton - San Jose CA, US
Hyun Kim - Sunnyvale CA, US
Swapneel Kekre - Sunnyvale CA, US
International Classification:
G06F 15/177
G06F 15/16
US Classification:
709229000, 709220000
Abstract:
An arrangement, in a computer system, for coordinating scheduling of threads on a processor associated with a scheduling-enabled entity. The arrangement includes a policy database of scheduling policies. The arrangement further includes an automatic policy selector associated with the scheduling-enabled entity. The automatic policy selector is configured to automatically select one of the scheduling policies responsive to a triggering event that includes at least one of a first event and a second event. The first event represents a change in configuration of the scheduling-enabled entity and the second event represents a policy selection from a human operator. One of the scheduling policies is employed to schedule the threads on the processors after being selected by the automatic policy selector.
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Swapneel A Kekre from Sunnyvale, CA, age ~47 Get Report