Search

Suresh K Upadhyayula

from San Jose, CA
Age ~71
Get Report
Also known as:
Suresh Kumar Upadhyayula, Suresh Usha Upadhyayula, Suresh Te Upadhyayula, Suresh A
Phone and address:
5895 Friar Way, San Jose, CA 95129
(408) 255-3730
Related to:
Pavan UpadhyayulaAditya K Upadhyayula, 36Usha Upadhyayula, 62A Upadhyayula
Connected to:
Aditya P Upadhyay, 30Akhilesh Upadhyay, 60Alok K Upadhyaya, 60Amit Upadhyaya, 48Anu Upadhyay, 32Apala Upadhyay, 37Apurva B Upadhyay, 40Arun K Upadhyaya, 71Bharat B Upadhyay, 76Bina Upadhyay, 69

Suresh Upadhyayula Phones & Addresses

  • 5895 Friar Way, San Jose, CA 95129 (408) 255-3730
  • 2679 Glen Fenton Way, San Jose, CA 95148
  • 6989 Chantel Ct, San Jose, CA 95129
  • Fremont, CA
  • 7232 Firelands Dr, Hudson, OH 44236 (330) 653-8121
  • Sunnyvale, CA
  • Fairfield, CA
  • Cupertino, CA
  • 5895 Friar Way, San Jose, CA 95129 (619) 701-3476

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Emails

s***[email protected]

Publications

Us Patents

Electrical Connector With Grounding Pin

View page
US Patent:
7354314, Apr 8, 2008
Filed:
Dec 29, 2006
Appl. No.:
11/618084
Inventors:
Steven Sprouse - San Jose CA, US
Ka Ian Yung - Mountain View CA, US
Suresh Upadhyayula - San Jose CA, US
Patricio Collantes - San Jose CA, US
Assignee:
SanDisk Corporation - Milpitas CA
International Classification:
H01R 24/00
US Classification:
439660
Abstract:
A semiconductor device is disclosed including a sheathless connector having a grounding pin which protects against electrical shorts and damage upon a backwards insertion of the connector to a host device. If the electrical connector is inserted backwards, the grounding pin mates with the signal ground terminal of the socket, and avoids contact with the remaining terminals. As a result, the damage otherwise occurring upon a backwards insertion of prior art devices is avoided.

Method Of Assembling Semiconductor Devices With Leds

View page
US Patent:
7384817, Jun 10, 2008
Filed:
May 13, 2005
Appl. No.:
11/129637
Inventors:
Hem Takiar - Fremont CA, US
Suresh Upadhyayula - San Jose CA, US
Assignee:
SanDisk Corporation - Milpitas CA
International Classification:
H01L 21/00
US Classification:
438106, 438 26, 438460, 438113
Abstract:
Methods of forming integrated circuit packages having an LED molded into the package, and the integrated circuit package formed thereby. An integrated circuit including one or more semiconductor die, passive components and an LED may be assembled on a panel. The one or more semiconductor die, passive components and LED may all then be encapsulated in a molding compound, and the integrated circuits then singularized to form individual integrated circuit packages. The integrated circuits are cut from the panel so that a portion of the lens of the LED is severed during the singularization process, and an end of the lens remaining within the package lies flush with an edge of the package to emit light outside of the package.

Method Of Assembling Semiconductor Devices With Leds

View page
US Patent:
7812356, Oct 12, 2010
Filed:
Apr 24, 2008
Appl. No.:
12/108837
Inventors:
Hem Takiar - Fremont CA, US
Suresh Upadhyayula - San Jose CA, US
Assignee:
SanDisk Corporation - Milpitas CA
International Classification:
H01L 27/15
H01L 29/161
H01L 31/12
H01L 31/153
H01L 33/00
US Classification:
257 84, 257 79, 257 81, 257100
Abstract:
Methods of forming integrated circuit packages having an LED molded into the package, and the integrated circuit package formed thereby. An integrated circuit including one or more semiconductor die, passive components and an LED may be assembled on a panel. The one or more semiconductor die, passive components and LED may all then be encapsulated in a molding compound, and the integrated circuits then singularized to form individual integrated circuit packages. The integrated circuits are cut from the panel so that a portion of the lens of the LED is severed during the singularization process, and an end of the lens remaining within the package lies flush with an edge of the package to emit light outside of the package.

Semiconductor Package Including Flip Chip Controller At Bottom Of Die Stack

View page
US Patent:
7867819, Jan 11, 2011
Filed:
Dec 27, 2007
Appl. No.:
11/965702
Inventors:
Suresh Upadhyayula - San Jose CA, US
Hem Takiar - Fremont CA, US
Assignee:
SanDisk Corporation - Milpitas CA
International Classification:
H01L 21/44
H01L 21/48
US Classification:
438107, 438108, 438109, 257E23169, 257E21614
Abstract:
A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations.

Etched Surface Mount Islands In A Leadframe Package

View page
US Patent:
8008132, Aug 30, 2011
Filed:
Dec 28, 2007
Appl. No.:
11/966303
Inventors:
Suresh Upadhyayula - San Jose CA, US
Bonnie Ming-Yan Chan - Sunnyvale CA, US
Shih-Ping Fan-chiang - Taichung, TW
Hem Takiar - Fremont CA, US
Assignee:
SanDisk Technologies Inc. - Plano TX
International Classification:
H01L 21/00
US Classification:
438123, 438113, 438124, 438108, 438111, 257667, 257E21506, 257E23052, 257E23106
Abstract:
A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package includes a leadframe and one or more semiconductor die affixed to a die paddle of the leadframe. The leadframe is formed with a plurality of electrical terminals that get surface mounted to a host PCB. The leadframe further includes one or more extended leads, at least one of which includes an electrically conductive island which gets surface mounted to the host PCB with the electrical terminals. The islands effectively increase the number terminals within the package without adding footprint to the package.

Method Of Assembling Semiconductor Devices With Leds

View page
US Patent:
8022417, Sep 20, 2011
Filed:
Oct 11, 2010
Appl. No.:
12/901787
Inventors:
Hem Takiar - Fremont CA, US
Suresh Upadhyayula - San Jose CA, US
Assignee:
SanDisk Technologies Inc. - Plano TX
International Classification:
H01L 27/15
H01L 29/161
H01L 31/12
H01L 31/153
H01L 33/00
US Classification:
257 84, 257 79, 257 81, 257100
Abstract:
Methods of forming integrated circuit packages having an LED molded into the package, and the integrated circuit package formed thereby. An integrated circuit including one or more semiconductor die, passive components and an LED may be assembled on a panel. The one or more semiconductor die, passive components and LED may all then be encapsulated in a molding compound, and the integrated circuits then singularized to form individual integrated circuit packages. The integrated circuits are cut from the panel so that a portion of the lens of the LED is severed during the singularization process, and an end of the lens remaining within the package lies flush with an edge of the package to emit light outside of the package.

Semiconductor Package Including Flip Chip Controller At Bottom Of Die Stack

View page
US Patent:
8373268, Feb 12, 2013
Filed:
Jan 7, 2011
Appl. No.:
12/986927
Inventors:
Suresh Upadhyayula - San Jose CA, US
Hem Takiar - Fremont CA, US
Assignee:
SanDisk Technologies Inc. - Plano TX
International Classification:
H01L 23/34
H01L 23/48
US Classification:
257723, 257686, 257777, 257E23169
Abstract:
A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations.

Col-Based Semiconductor Package Including Electrical Connections Through A Single Layer Leadframe

View page
US Patent:
8575739, Nov 5, 2013
Filed:
May 6, 2011
Appl. No.:
13/102291
Inventors:
Suresh Upadhyayula - San Jose CA, US
Ming Hsun Lee - Taichung, TW
Hem Takiar - Fremont CA, US
Assignee:
SanDisk Technologies Inc. - Plano TX
International Classification:
H01L 23/02
US Classification:
257679, 257666, 257676, 257686, 257723, 257777
Abstract:
A semiconductor package is disclosed including a leadframe, memory die and controller die, one or more of which are customized to facilitate electrical connection of the memory and controller die bond pads to the contact pads of the host device via the leadframe. By customizing one or more of the leadframe, memory die and controller die, an interposer layer normally required to connect the die in the semiconductor package with a host device may be omitted.
Control profile
Suresh K Upadhyayula from San Jose, CA, age ~71 Get Report