Sunil R Atri

7424643, Sep 9, 2008

Dec 30, 2004

11/025113

Sunil Atri - Folsom CA, US
Nicholas Woo - Albuquerque NM, US
Kurt Sowa - Shingle Springs CA, US
Ajith Illendula - Albuquerque NM, US

Intel Corporation - Santa Clara CA

G06F 11/00

714 22

A method, device and system for determining whether a prior shut down of a device having a solid state non-volatile memory unit such as a flash memory unit resulted from a power loss and disorderly shut down and whether a power loss recovery procedure should be run.

7675776, Mar 9, 2010

Dec 21, 2007

11/963286

Walter Allen - Wellington CO, US
Robert France - Austin TX, US
Sunil Atri - Austin TX, US

Spansion, LLC - Sunnyvale CA

G11C 16/06

36518509, 365200, 36518511

Systems and methods that facilitate bad block management in a memory device that comprises nonvolatile memory are presented. One or more memory blocks of a memory device are each associated with one or more additional, dedicated bits that facilitate indicating whether the associated memory block is defective. These additional bits, called bad block bits, can be stored in a hardware-based storage mechanism within the memory device. Once a defect is detected in a memory block, at least one of the associated bad block bits can be set to indicate that the memory block is defective. If at least one of the bad block bits associated with a memory block indicates a memory block is defective, access to the memory block can be prevented.

7949851, May 24, 2011

Dec 28, 2007

11/966919

Walter Allen - Austin TX, US
Sunil Atri - Austin TX, US
Robert France - Austin TX, US

Spansion LLC - Sunnyvale CA

G06F 12/00

711203, 711202, 711E12058

Systems and/or methods that facilitate PBA and LBA translations associated with a memory component(s) are presented. A memory controller component facilitates determining which memory component, erase block, page, and data block contains a PBA in which a desired LBA and/or associated data is stored. The memory controller component facilitates control of performance of calculation functions, table look-up functions, and/or search functions to locate the desired LBA. The memory controller component generates a configuration sequence based in part on predefined optimization criteria to facilitate optimized performance of translations. The memory controller component and/or associated memory component(s) can be configured so that the translation attributes are determined in a desired order using the desired translation function(s) to determine a respective translation attribute based in part on the predefined optimization criteria. The LBA to PBA translations can be performed in parallel by memory components.

7953919, May 31, 2011

Dec 21, 2007

11/963306

Walter Allen - Wellington CO, US
Sunil Atri - Austin TX, US
Joseph Khatami - Austin TX, US

Spansion LLC - Sunnyvale CA

G06F 12/06
G06F 13/00

711 1, 711100, 711103, 711154

Systems and/or methods that facilitate accessing data to/from a memory are presented. An electronic memory component can operate with reduced data access times by eliminating/reducing the use of logical block addressing and employing physical block addressing. Data access is thereby directly associated with the physical location of the stored bits and the need to translate between a logical address and the physical address is reduced or eliminated. This can be even more efficient under asymmetric data access patterns. Further, legacy support for logical block addressing can be included to provide backward compatibility, mixed mode operation, or complimentary mode operation.

8032787, Oct 4, 2011

Sep 2, 2004

10/933862

Sunil R Atri - Folsom CA, US
Sean S Eilert - Penryn CA, US

Intel Corporation - Santa Clara CA

G06F 11/00

714 22

According to some embodiments, power loss recovery information related to an active operation is stored in volatile memory. Upon detection of a power loss condition, the power loss recovery information is copied to non-volatile memory. Upon a return of power, the power loss recovery information is used to complete or correct the interrupted operation.

8239875, Aug 7, 2012

Dec 21, 2007

11/962918

Walter Allen - Wellington CO, US
Sunil Atri - Austin TX, US
Joseph Khatami - Austin TX, US

Spansion LLC - Sunnyvale CA

G06F 9/305

719314, 711103, 711127, 711157, 711168, 711169

Systems and/or methods that facilitate transferring data between a processor component and memory components are presented. A transfer controller component facilitates controlling data transfers in part by receiving respective subsets of data from respective memory components and arranging the respective subsets of data based in part on a desired predefined data order. The processor component generates a transfer map that includes information to facilitate arranging data in a predefined order. The processor component generates respective subsets of commands that are provided to queue components in respective memory components to retrieve desired data from the respective memory components. Each memory component services the commands in its queue component in an independent and parallel manner, and transfers the data retrieved from memory to the transfer controller component, which can arrange the received data in a predefined order for transfer to the processor component.

8464021, Jun 11, 2013

May 28, 2008

12/127919

Walter Allen - Wellington CO, US
Sunil Atri - Austin TX, US
Robert France - Austin TX, US

Spansion LLC - Sunnyvale CA

G06F 9/34
G06F 9/26

711202, 711103, 711118, 711221

Systems and/or methods that facilitate logical block address (LBA) to physical block address (PBA) translations associated with a memory component(s) are presented. The disclosed subject matter employs an optimized block address (BA) component that can facilitate caching the LBA to PBA translations within a memory controller component based in part on a predetermined optimization criteria to facilitate improving the access of data associated with the memory component. The predetermined optimization criteria can relate to a length of time since an LBA has been accessed, a number of times the LBA has been access, a data size of data related to an LBA, and/or other factors. The LBA to PBA translations can be utilized to facilitate accessing the LBA and/or associated data using the cached translation, instead of performing various functions to determine the translation.

20050071731, Mar 31, 2005

Sep 25, 2003

10/672998

Sunil Atri - Folsom CA, US
John Rudelic - Folsom CA, US

G11C029/00

714763000

A technique for coalesced PLR status bits in an ECC enabled flash memory.