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Sukhbir Singh Dulay

from Saratoga, CA
Age ~53
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Also known as:
Sukhbir S Dulay, Sukii Singii Dulay, Sukii S Dulay, Sukhbir S Dolay, Surhbir Dulay, Sukhbir Dulay Singh, R Dulay
Phone and address:
17871 Los Alamos Dr, Saratoga, CA 95070
Related to:
Tejinder Singh, 33Harminder Singh, 71Kulwant S Dhillon, 66Paraminder Singh, 71
Connected to:
Angel D Dulay, 91Arvin C Dulay, 49Avee D Dulay, 34Bernadette U Dulay, 52Brian W Dulay, 41Charles J Dulay, 80Christine M Dulay, 45Curtis L Dulay, 44Eduardo P Dulay, 72Elma Z Dulay, 59

Sukhbir Dulay Phones & Addresses

  • 17871 Los Alamos Dr, Saratoga, CA 95070
  • 6936 Gregorich Dr, San Jose, CA 95138
  • Sacramento, CA
  • Santa Clara, CA
  • Yuba City, CA
  • Davis, CA
  • 5015 Amondo Dr, San Jose, CA 95129

Work

Company: Formfactor Mar 2011 Position: Sr. engineering manager

Education

School / High School: University of California- Davis, CA Jun 1995 Specialities: Bachelor of Science in Chemical/Biochemical Engineering

Resumes

Resumes

Sukhbir Dulay Photo 1

Sukhbir Dulay San Jose, CA

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Work:
FormFactor

Mar 2011 to 2000
Sr. Engineering Manager
FormFactor
Livermore, CA
Nov 2005 to Mar 2011
Sr. Staff Process Engineer
IBM/HGST
San Jose, CA
Jun 2000 to Nov 2005
Staff Manufacturing Engineer
Vigobyte International
Sunnyvale, CA
Apr 1999 to Jun 2000
Manufacturing Engineer
Applied Magnetics Corporation
Goleta, CA
Jun 1997 to Dec 1998
Manufacturing Engineer
Education:
University of California
Davis, CA
Jun 1995
Bachelor of Science in Chemical/Biochemical Engineering

Publications

Us Patents

Method Of Fabricating Thin Film Calibration Features For Electron/Ion Beam Image Based Metrology

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US Patent:
7323350, Jan 29, 2008
Filed:
Sep 30, 2004
Appl. No.:
10/957097
Inventors:
Sukhbir Singh Dulay - San Jose CA, US
Justin Jia-Jen Hwu - San Jose CA, US
Thao John Pham - San Jose CA, US
Assignee:
Hitachi Global Storage Technologies Netherlands B.V. - Amsterdam
International Classification:
H01L 21/00
H01L 23/58
US Classification:
438 10, 438 17, 257 48
Abstract:
A method of making and using thin film calibration features is described. To fabricate a calibration standard according to the invention raised features are first formed from an electrically conductive material with a selected atomic number. A conformal thin film layer is deposited over the exposed sidewalls of the raised features. The sidewall material is selected to have a different atomic number and is preferably an nonconductive such as silicon dioxide or alumina. After the nonconductive material deposition, a controlled directional RIE process is used to remove the insulator layer deposited on the top and bottom surface of the lines and trenches. The remaining voids between the sidewalls of the raised features are filled with a conductive material. The wafer is then planarized with chemical mechanical planarization (CMP) to expose the nonconductive sidewall material on the surface. The nonconductive sidewall material will be fine lines embedded in conductive material.

Method For Manufacturing A Magnetic Write Head

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US Patent:
7454828, Nov 25, 2008
Filed:
Nov 23, 2005
Appl. No.:
11/286076
Inventors:
Sukhbir Singh Dulay - San Jose CA, US
Justin Jia-Jen Hwu - San Jose CA, US
Thao John Pham - San Jose CA, US
Assignee:
Hitachi Global Storage Technologies Netherlands B.V. - Amsterdam
International Classification:
G11B 5/127
H04R 31/00
US Classification:
2960316, 2960313, 2960315, 2960318, 216 62, 216 65, 216 66, 20419234, 360122, 360317, 451 5, 451 41
Abstract:
A method for measuring recession in a wafer undergoing an asymmetrical ion mill process. The method includes the formation of first and second reference features and possibly a dummy feature. The reference features are constructed such that the location of the midpoint between them is unaffected by the asymmetrical ion mill. By measuring the distance between a portion of the dummy feature and the midpoint between the reference features, the amount of recession of the dummy feature can be measured. The measurement can be used to calculate the relative location of the flare to the read sensor rear edge through overlay information. By keeping the angles of the sides of the features steep (ie. nearly parallel with the direction in which the ion mill is asymmetrical) the amount of material consumed on each of the reference features is substantially equal and the midpoint between the reference features is substantially stationary.

Cmp Process Metrology Test Structures

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US Patent:
20060068511, Mar 30, 2006
Filed:
Sep 30, 2004
Appl. No.:
10/956452
Inventors:
Sukhbir Dulay - San Jose CA, US
Thomas Leong - San Jose CA, US
John Yang - Newark CA, US
International Classification:
H01L 21/66
US Classification:
438014000
Abstract:
A method for forming metrology structures for a CMP process is described. A trench edge is formed in a base material or stack of materials which are preferably deposited as part of the process of fabricating the production structures on the wafer. A covering film of a second material with preferably with contrasting SEM properties is deposited over the trench edge in the base material. During CMP the covering film is preferentially worn away at the edge revealing the base material. The width of the base material which has been revealed is a measure of the progress of the CMP. Since the base material and the covering material are preferably selected to have contrasting images in an SEM, a CD-SEM can be used to precisely measure the CMP progress.
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Sukhbir Singh Dulay from Saratoga, CA, age ~53 Get Report