Search

Steven P Radigan

from Bloomington, IN
Age ~42
Get Report
Also known as:
Steven Patrick Radigan, Steve Radigan
Related to:
Est A RadiganMaureen A Radigan, 38Maria Radigan, 73Patrick Radigan, 74
Connected to:
Fallon M Radigan, 40Justin E Radigan, 46Kerry Radigan, 31Lois M Radigan, 84Nicole Radigan, 44Tera L Radigan, 47Tom A Radigan, 53Jennifer E Radik, 34Jesse Radika, 53Thomas R Radikin, 50

Steven Radigan Phones & Addresses

  • Bloomington, IN
  • San Jose, CA
  • 7073 Academy Ln, Lockport, NY 14094 (716) 433-7832

Resumes

Resumes

Steven Radigan Photo 1

Systems Engineer

View page
Location:
3801 Fairhaven Dr, Fort Worth, TX 76123
Industry:
Defense & Space
Work:
Us Navy
Systems Engineer
Mga Research Co. Apr 2004 - Jan 2005
Electrical Engineer
Education:
Naval Postgraduate School 2009 - 2011
Masters, Master of Science In Software Engineering, Engineering University at Buffalo 1999 - 2003
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering
Skills:
Systems Engineering
Earned Value Management
Dod
Electrical Engineering
Engineering Management
Electronics
Requirements Analysis
Embedded Systems
Security Clearance
Interests:
Electric Skateboard
Electric Bicycle Design
Steven Radigan Photo 2

Engineer

View page
Location:
Bloomington, IN
Industry:
Semiconductors
Work:
Navy Federal Credit Union
Engineer
Steven Radigan Photo 3

Steven Radigan

View page

Publications

Us Patents

Structure, Fabrication, And Corrective Test Of Electron-Emitting Device Having Electrode Configured To Reduce Cross-Over Capacitance And/Or Facilitate Short-Circuit Repair

View page
US Patent:
6734620, May 11, 2004
Filed:
Dec 12, 2001
Appl. No.:
10/017656
Inventors:
Steven J. Radigan - Fremont CA
Matthew A. Bonn - Saratoga CA
Hidenori Kemmotsu - San Jose CA
Theodore S. Fahlen - San Jose CA
Assignee:
Candescent Technologies Corporation - Los Gatos CA
Candescent Intellectual Property Services, Inc. - Los Gatos CA
Sony Corporation - Tokyo
International Classification:
H01J 130
US Classification:
313497, 313310, 445 24
Abstract:
An electron-emitting device ( , or ) contains an electrode, either a control electrode ( ) or an emitter electrode ( ), having a specified portion situated off to the side of the bulk of the electrode. For a control electrode, the specified portion is an exposure portion ( EA or EB) having openings that expose electron-emissive elements ( A or B) situated over an emitter electrode. For an emitter electrode, the specified portion is an emitter-coupling portion situated below at least one electron-emissive element exposed through at least one opening in a control electrode. Configuring the device in this way enables the control-electrode-to-emitter-electrode capacitance to be quite small, thereby enhancing the devices switching speed. If the specified portion of the electrode becomes short circuited to the other electrode, the short-circuit defect can be removed by severing the specified portion from the remainder of its electrode.

Metal Structures For Integrated Circuits And Methods For Making The Same

View page
US Patent:
7018878, Mar 28, 2006
Filed:
Nov 7, 2001
Appl. No.:
10/045653
Inventors:
Michael A. Vyvoda - Fremont CA, US
Steven J. Radigan - Fremont CA, US
K. Leo Zhang - Shanghai, CN
Assignee:
Matrix Semiconductor, Inc. - Santa Clara CA
International Classification:
H01L 21/336
US Classification:
438197, 438597
Abstract:
Metal structures for ICs and methods for manufacturing the same are described. The metal structures range from small features to large features and are resistant to peeling problems during heat treatments that occur during the manufacturing process. Peeling of the metal structures from the underlying structures or substrates is reduced or prevented. The peeling problems are reduced or prevented by including a capping layer or capping structure over the dielectric layer over the metal structure and then annealing the capping layer or capping structure, thereby enhancing the adhesion of the metal structure to the underlying structure or substrate.

Nonvolatile Memory Cell Comprising A Reduced Height Vertical Diode

View page
US Patent:
7285464, Oct 23, 2007
Filed:
Dec 17, 2004
Appl. No.:
11/015824
Inventors:
S. Brad Herner - San Jose CA, US
Steven J. Radigan - Fremont CA, US
Assignee:
Sandisk 3D LLC - Milpitas CA
International Classification:
H01L 21/336
US Classification:
438258, 438257, 438593, 438594, 257314, 257315
Abstract:
A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped region, and a top heavily doped region, wherein the conductivity types of the top and bottom heavily doped region are opposite. The junction diode is vertically oriented and is of reduced height, between about 500 angstroms and about 3500 angstroms. A monolithic three dimensional memory array of such cells can be formed comprising multiple memory levels, the levels monolithically formed above one another.

Method For Cleaning Slurry Particles From A Surface Polished By Chemical Mechanical Polishing

View page
US Patent:
7300876, Nov 27, 2007
Filed:
Dec 14, 2004
Appl. No.:
11/013067
Inventors:
Samuel V. Dunton - San Jose CA, US
Steven J. Radigan - Fremont CA, US
Assignee:
Sandisk 3D LLC - Milpitas CA
International Classification:
H01L 21/302
US Classification:
438692, 438959, 438582
Abstract:
A method is provided to clean slurry particles from a surface in which tungsten and dielectric are coexposed after a dielectric CMP step. Such a surface is formed when tungsten features are patterned and etched, the tungsten features are covered with dielectric, and the dielectric is planarized to expose tops of the tungsten features. The surface to be cleaned is subjected to mechanical action in an acid environment. Suitable mechanical action includes performing a brief tungsten CMP step on the tungsten features or scrubbing the surface using, for example, a commercial post-CMP scrubber.

Masking Of Repeated Overlay And Alignment Marks To Allow Reuse Of Photomasks In A Vertical Structure

View page
US Patent:
7553611, Jun 30, 2009
Filed:
Mar 31, 2005
Appl. No.:
11/097496
Inventors:
Yung-Tin Chen - Santa Clara CA, US
Christopher J Petti - Mountain View CA, US
Steven J Radigan - Fremont CA, US
Tanmay Kumar - Pleasanton CA, US
Assignee:
Sandisk 3D LLC - Milpitas CA
International Classification:
G03C 5/00
G03C 1/00
US Classification:
430394, 430 5
Abstract:
In formation of monolithic three dimensional memory arrays, a photomask may be used more than once. Reuse of a photomask creates second, third or more instances of reference marks used by the stepper to achieve alignment (alignment marks) and to measure alignment achieved (overlay marks) directly above prior instances of the same reference mark. The prior instances of the same reference mark may cause interference with the present instance of the reference mark, complicating alignment and measurement. Using the methods of the present invention, blocking structure is created vertically interposed between subsequent instances of the same reference mark, preventing interference.

Nonvolatile Memory Cell Comprising A Reduced Height Vertical Diode

View page
US Patent:
7560339, Jul 14, 2009
Filed:
Oct 2, 2007
Appl. No.:
11/866403
Inventors:
S. Brad Herner - San Jose CA, US
Steven J. Radigan - Fremont CA, US
Assignee:
Sandisk 3D LLC - Milpitas CA
International Classification:
H01L 29/80
US Classification:
438258, 438257, 438593, 438E23147, 438E29091
Abstract:
A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped region, and a top heavily doped region, wherein the conductivity types of the top and bottom heavily doped region are opposite. The junction diode is vertically oriented and is of reduced height, between about 500 angstroms and about 3500 angstroms. A monolithic three dimensional memory array of such cells can be formed comprising multiple memory levels, the levels monolithically formed above one another.

Conductive Hard Mask To Protect Patterned Features During Trench Etch

View page
US Patent:
7575984, Aug 18, 2009
Filed:
May 31, 2006
Appl. No.:
11/444936
Inventors:
Steven J Radigan - Fremont CA, US
Usha Raghuram - San Jose CA, US
Samuel V Dunton - San Jose CA, US
Michael W Konevecki - San Jose CA, US
Assignee:
Sandisk 3D LLC - Milpitas CA
International Classification:
H01L 21/326
H01L 21/82
H01L 21/44
US Classification:
438467, 438131, 438600, 438700
Abstract:
A method is provided for forming patterned features using a conductive hard mask, where the conductive hard mask protects those features during a subsequent trench etch to form Damascene conductors providing electrical connection to those features from above. The thickness of the hard mask provides a margin to avoid overetch during the trench etch which may be harmful to device performance. The method is advantageously used in formation of a monolithic three dimensional memory array.

Method For Reducing Pillar Structure Dimensions Of A Semiconductor Device

View page
US Patent:
7682942, Mar 23, 2010
Filed:
Sep 28, 2007
Appl. No.:
11/864205
Inventors:
Yung-Tin Chen - Santa Clara CA, US
Michael Chan - Mountain View CA, US
Paul Poon - Fremont CA, US
Steven J. Radigan - Fremont CA, US
Assignee:
Sandisk 3D LLC - Milpitas CA
International Classification:
H01L 21/20
H01L 21/36
US Classification:
438478, 257613
Abstract:
A method creates pillar structures on a semiconductor wafer and includes the steps of providing a layer of semiconductor. A layer of photoresist is applied over the layer of semiconductor. The layer of photoresist is exposed with an initial pattern of light to effect the layer of photoresist. The photoresist layer is then etched away to provide a photoresist pattern to create the pillar structures. The photoresist pattern is processed in the layer of photoresist after the step of exposing the layer of photoresist and prior to the step of etching to reduce the dimensions of the photoresist pattern in the layer of photoresist.
Control profile
Steven P Radigan from Bloomington, IN, age ~42 Get Report