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Sridhar Te Begur

from Vista, CA
Age ~66
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Also known as:
Sridhar B Begur, Sridhar S Begur, Shridhar Begur, Begur Sridhar
Related to:
Manali BegurA BegurMeghana BegurSashikala Begur, 66
Connected to:
Sachi V Begur, 60Bradford G Begy, 50Kevin V Begy, 50Alan K Begyn, 56Brent T Begyn, 39Betty B Beh, 64Chu M Beh, 60Evelyn Beh, 44Hock L Beh, 81Jessie D Beh, 104

Sridhar Begur Phones & Addresses

  • Vista, CA
  • 21410 Columbus Ave, Cupertino, CA 95014 (408) 863-0345 (408) 863-1234
  • San Jose, CA
  • Sunnyvale, CA
  • Fair Oaks, CA

Resumes

Resumes

Sridhar Begur Photo 1

Vice President, Phy

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Location:
San Francisco, CA
Industry:
Computer Networking
Work:
Plx Technologies
Vice President, Phy
Sridhar Begur Photo 2

Sridhar Begur

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Publications

Us Patents

Method And Apparatus For A X-Dsl Communication Processor

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US Patent:
6940807, Sep 6, 2005
Filed:
Oct 26, 2000
Appl. No.:
09/699193
Inventors:
Behrooz Rezvani - Pleasanton CA, US
Avadhani Shridhar - Santa Clara CA, US
Raminder S. Bajwa - Palo Alto CA, US
Tiruvur R. Ramesh - Union City CA, US
Masoud Eskandari - San Jose CA, US
Firooz Massoudi - Santa Clara CA, US
Sam Heidari - Fremont CA, US
Omprakash S. Sarmaru - Fremont CA, US
Sridhar Begur - Cupertino CA, US
Assignee:
Velocity Communication, Inc. - Fremont CA
International Classification:
H04J011/00
US Classification:
370210, 370352
Abstract:
The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) portions across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session. The DSP offers the speed associated with hardware implementation of the transforms and the flexibility of a software only implementation. Traffic flow is regulated in the chip using a packet based schema in which each packet is associated with a specific channel of upstream and downstream data. Header and control information in each packet is used to govern the processing of each packet as it moves along either the transmit path or receive path. The DSP of the current invention may advantageously be utilized in fields other than communications, such as: medical and other imaging, seismic analysis, radar and other military applications, pattern recognition, signal processing etc.

Method And Apparatus For A Dft/Idft Engine Supporting Multiple X-Dsl Protocols

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US Patent:
7028063, Apr 11, 2006
Filed:
Oct 26, 2000
Appl. No.:
09/698824
Inventors:
Omprakash S. Sarmaru - Fremont CA, US
Raminder S. Bajwa - Palo Alto CA, US
Sridhar Begur - Cupertino CA, US
Avadhani Shridhar - Santa Clara CA, US
Sam Heid Ari - Fremont CA, US
Behrooz Rezvani - Pleasanton CA, US
Assignee:
Velocity Communication, Inc. - Fremont CA
International Classification:
F06F 17/14
US Classification:
708403, 708406, 708404
Abstract:
A Fourier transform processor utilizing discrete circuits each of which is configurable for processing a wide range of sample sizes. A single pipeline supports multiplexed bi-directional transformations between for example the time and frequency domains. In an embodiment of the invention the Fourier Transform processor may be implemented as part of a digital signal processor (DSP). In this embodiment the DSP may implement both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session.

System And Method For Shadowing And Re-Mapping Reserved Memory In A Microcomputer

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US Patent:
52029948, Apr 13, 1993
Filed:
Jan 31, 1990
Appl. No.:
7/472057
Inventors:
Sridhar Begur - San Jose CA
Irvin R. Jones - San Jose CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1216
US Classification:
395700
Abstract:
A system and method for managing the reserved memory in a microcomputer copies selected portions of reserved memory to a new reserved memory having a faster access time, and allows any free portions of the new reserved memory to be accessed by a typical software application. After the selected portions of reserved memory are copied, all access to an address within a selected portion are re-directed to the new reserved memory. Any free portions of new reserved memory have additional, accessible memory re-mapped to these free portions.

Microprocessor Burst Mode With External System Memory

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US Patent:
57324069, Mar 24, 1998
Filed:
Sep 23, 1992
Appl. No.:
7/950979
Inventors:
Carol Elise Bassett - Cupertino CA
Robert Gregory Campbell - Santa Clara CA
Marilyn Jean Lang - Milpitas CA
Sridhar Begur - San Jose CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1314
US Classification:
711104
Abstract:
A microcomputer architecture and method allows for high processing speeds. A microprocessor constitutes the central processing unit. The microprocessor comprises an on-chip cache memory and is capable of reading data in a burst mode. The central processing unit and the system memory communicate by way of a high speed host bus. The system memory is comprised of multiple buses and is capable of delivering data to the microprocessor in a burst mode at high speeds. A memory controller addresses data locations within the system memory upon receipt of a first host address from the microprocessor. Accordingly, the microprocessor can access data in the system memory at an extremely fast rate when operating in a burst mode. High speed processing is accomplished without the need for an external cache.

System And Method For Shadowing And Re-Mapping Reserved Memory In A Microcomputer

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US Patent:
53013280, Apr 5, 1994
Filed:
Sep 25, 1992
Appl. No.:
7/951650
Inventors:
Sridhar Begur - San Jose CA
Irvin R. Jones - San Jose CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1202
US Classification:
395700
Abstract:
A system and method for managing the reserved memory in a microcomputer copies selected portions of reserved memory to a new reserved memory having a faster access time, and allows any free portions of the new reserved memory to be accessed by a typical software application. After the selected portions of reserved memory are copied, all access to an address within a selected portion are re-directed to the new reserved memory. Any free portions of new reserved memory have additional, accessible memory re-mapped to these free portions.

System And Method For Accessing Data Between A Host Bus And System Memory Buses In Which Each System Memory Bus Has A Data Path Which Is Twice The Width Of The Data Path For The Host Bus

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US Patent:
59604506, Sep 28, 1999
Filed:
Dec 24, 1992
Appl. No.:
7/997620
Inventors:
Marilyn Jean Lang - Milpitas CA
Sridhar Begur - San Jose CA
Robert Campbell - Santa Clara CA
Carol Elise Bassett - Cupertino CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1202
US Classification:
711 5
Abstract:
A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.

Multiple Parallel Digital Data Stream Channel Controller Architecture

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US Patent:
58225536, Oct 13, 1998
Filed:
Mar 13, 1996
Appl. No.:
8/614729
Inventors:
James K. Gifford - Danville CA
Sridhar Begur - San Jose CA
Adrian Lewis - Fremont CA
Donald J. Spencer - San Jose CA
Thomas E. Kilbourn - Saratoga CA
Daniel B. Gochnauer - Saratoga CA
Assignee:
Diamond Multimedia Systems, Inc. - San Jose CA
International Classification:
G06F 800
US Classification:
395309
Abstract:
A multiple data stream channel controller providing demand driven transport of multiple data streams concurrently in real time through a peripheral data channel coupled between a general purpose processor system and a special purpose processor system. The controller comprises a first bus master interface coupleable to a general purpose processor system bus, a second bus master interface coupleable to a special purpose processor system bus, a segmentable buffer memory and a controller that directs the transfer of data segments between the first and second bus master interfaces via the segmentable buffer memory. The controller is responsive to a plurality of signals provided by the special purpose processor bus to request transfer of successive data segments from a respective plurality of data streams staged in the segmentable buffer memory. The controller moderates the transfer of successive data segments of the respective plurality of data streams via the first bus master interface to the segmentable buffer memory.

System And Method For Accessing Data Between A Host Bus And A System Memory Bus Where The System Memory Bus Has A Data Path That Is Twice The Width Of The Data Path For The Host Bus

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US Patent:
62021206, Mar 13, 2001
Filed:
Jul 30, 1999
Appl. No.:
9/364480
Inventors:
Marilyn Jean Lang - Milpitas CA
Sridhar Begur - San Jose CA
Robert Campbell - Santa Clara CA
Carol Elise Bassett - Cupertino CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1202
US Classification:
711 5
Abstract:
A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.
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Sridhar Te Begur from Vista, CA, age ~66 Get Report