US Patent:
20160179546, Jun 23, 2016
Inventors:
- Santa Clara CA, US
PALANIVELRAJAN SHANMUGAVELAYUTHAM - San Jose CA, US
SRAVANI KONDA - San Jose CA, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
G06F 9/38
G06F 9/30
Abstract:
Various embodiments are generally directed to an apparatus, method and other techniques to determine a valid target address for a branch instruction from information stored in a relocation table, a linkage table, or both, the relocation table and the linkage table associated with a binary file and store the valid target address in a table in memory, the valid target address to validate a target address for a translated portion of a routine of the binary file.