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Smeeta Jain Gupta

from Saratoga, CA
Age ~64
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Also known as:
Smeeta Te Gupta, Smeeta Jain, Meeta Gupta, Anil Gupta
Phone and address:
19444 De Havilland Dr, Saratoga, CA 95070
(408) 255-3325
Related to:
Divya G Burton, 48Horace Burton, 66Karmiko R Burton, 52Promila GuptaDiana Burton, 70Margaret Burton, 37
Connected to:
Aashish Gupta, 45Abhijat A Gupta, 43Ajaya Gupta, 64Ajaykumar K Gupta, 58Akriti Gupta, 35Akshey Gupta, 47Alankar A Gupta, 84Amartya S Gupta, 45Amitesh K Gupta, 45Amitkumar N Gupta, 44

Smeeta Gupta Phones & Addresses

  • 19444 De Havilland Dr, Saratoga, CA 95070 (408) 255-3325
  • Irvine, CA
  • Phoenix, AZ
  • Cupertino, CA
  • Sunnyvale, CA
  • Orange, CA

Work

Company: Ampere computing May 2018 Position: Architectural design verification manager

Education

School / High School: De Anza College 2010 to 2011 Specialities: Law

Skills

Uvm • Functional Verification • Asic • Processors • Ic • Computer Architecture • Perl • C • Semiconductor Industry • Debugging • Microprocessors • Embedded Systems • Arm • Simulations • Soc

Industries

Computer Hardware

Resumes

Resumes

Smeeta Gupta Photo 1

Architectural Design Verification Manager

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Location:
San Francisco, CA
Industry:
Computer Hardware
Work:
Ampere Computing
Architectural Design Verification Manager
Amd 2003 - 2009
Staff Engineer Design Verification
Artile Micro Systems Jan 2002 - Jan 2003
Senior Software Design Engineer
Clear Water Networks 2000 - 2002
Senior Verification Engineer
Siemens/Infineon 1995 - 1999
Verification Engineer
Education:
De Anza College 2010 - 2011
Santa Clara University 1983 - 1987
University of Colorado Boulder 1976 - 1980
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Uvm
Functional Verification
Asic
Processors
Ic
Computer Architecture
Perl
C
Semiconductor Industry
Debugging
Microprocessors
Embedded Systems
Arm
Simulations
Soc

Business Records

Name / Title
Company / Classification
Phones & Addresses
Smeeta Gupta
President
MEETA ASSOCIATES INC
19444 Dehavillard Dr, Saratoga, CA 95070
19444 De Havilland Dr, Saratoga, CA 95070

Publications

Us Patents

Normalizing Pipelined Floating Point Processing Unit

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US Patent:
50580485, Oct 15, 1991
Filed:
Apr 2, 1990
Appl. No.:
7/503819
Inventors:
Smeeta Gupta - Saratoga CA
Robert M. Perlman - San Jose CA
Thomas W. Lynch - Austin TX
Brian D. McMinn - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 738
US Classification:
364748
Abstract:
A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When an denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent.

Streamlined Instruction Processor

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US Patent:
49263234, May 15, 1990
Filed:
Mar 3, 1988
Appl. No.:
7/163917
Inventors:
Gigy Baror - Austin TX
Brian W. Case - Sunnyvale CA
Rod G. Fleck - Munich, DE
Philip M. Freidin - Sunnyvale CA
Smeeta Gupta - Saratoga CA
William M. Johnson - San Jose CA
Cheng-Gang Kong - Saratoga CA
Ole H. Moller - Lyngby, DK
Timothy A. Olson - Sunnyvale CA
David I. Sorensen - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 940
G06F 900
US Classification:
364200
Abstract:
A streamlined instruction processor processes data in response to a program composed of prespecified instructions in pipeline cycles. The processor comprises an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions from the instruction memory. The instruction fetch unit includes an instruction prefetch buffer coupled to the instruction interface for buffering a sequence of instructions supplied to the instruction interface. A branch target cache is coupled with the prefetch buffer for storing sets of instructions retrieved from a corresponding set of locations in the instruction memory, having sequential instruction addresses. The first instruction in each such set is a branch target instruction in the program. In addition, an execution unit including a data interface adapted for connection to the data memory, executes the instructions in pipeline cycles.

Normalizing Pipelined Floating Point Processing Unit

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US Patent:
52671860, Nov 30, 1993
Filed:
Jul 23, 1991
Appl. No.:
7/734762
Inventors:
Smeeta Gupta - Saratoga CA
Robert M. Perlman - San Jose CA
Thomas W. Lynch - Austin TX
Brian D. McMinn - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 738
US Classification:
364748
Abstract:
A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When a denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent.
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Smeeta Jain Gupta from Saratoga, CA, age ~64 Get Report