Siva K Kanakasabapathy from 284 Sullivan Ct, Pleasanton, CA 94566, age 50, Phone: (518) 372-1248

Particle Contamination Cleaning From Substrates Using Plasmas, Reactive Gases, And Mechanical Agitation

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US Patent:

6676800, Jan 13, 2004

Filed:

Mar 15, 2000

Appl. No.:

09/525556

Inventors:

John J. Festa - McKinney TX
Darryl Bennett - Dallas TX
Joel Brad Bailey - Dallas TX
Lawrence J. Overzet - Plano TX
Marwan H. Khater - Dallas TX
Siva K. Kanakasabapathy - Richardson TX

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H05H 100

US Classification:

156345, 134 11, 134 12

Abstract:

A method and apparatus for cleaning semiconductor wafers, next generation lithography (NGL) masks, and optical photomasks as well as test wafers and in service NGL and optical masks is disclosed. The method and apparatus utilize reactive gases and gas mixtures and mechanical agitation to enhance particle removal. The addition of a reactive gas process to an inert gas feed enhances the plasma cleaning process by breaking chemical bonds which form between surface particles and a substrate, consequently improving cleaning efficiency.

Finfet Gate Cut After Dummy Gate Removal

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US Patent:

20200243648, Jul 30, 2020

Filed:

Feb 21, 2020

Appl. No.:

16/798240

Inventors:

- San Jose CA, US
Siva Kanakasabapathy - Pleasanton CA, US
Andrew M. Greene - Albany NY, US
Jeffrey Shearer - Albany NY, US
Nicole A. Saulnier - Albany NY, US

Assignee:

TESSERA, INC. - San Jose CA

International Classification:

H01L 29/10
H01L 21/8234
H01L 21/8238
H01L 29/66
H01L 27/088
H01L 29/78
H01L 27/092
H01L 21/02
H01L 25/065
H01L 29/417

Abstract:

Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.

Gate Cut In Rmg

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US Patent:

20200044051, Feb 6, 2020

Filed:

Oct 11, 2019

Appl. No.:

16/599164

Inventors:

- Armonk NY, US
Siva Kanakasabapathy - Pleasanton CA, US
Andrew M. Greene - Albany NY, US

International Classification:

H01L 29/66
H01L 21/768
H01L 21/027
H01L 27/088
H01L 21/306
H01L 21/8234
H01L 21/8238
H01L 29/78
H01L 21/308
H01L 21/762

Abstract:

A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.

Gate Cut In Rmg

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US Patent:

20200044052, Feb 6, 2020

Filed:

Oct 11, 2019

Appl. No.:

16/599229

Inventors:

- Armonk NY, US
Siva Kanakasabapathy - Pleasanton CA, US
Andrew M. Greene - Albany NY, US

International Classification:

H01L 29/66
H01L 21/768
H01L 21/027
H01L 27/088
H01L 21/306
H01L 21/8234
H01L 21/8238
H01L 29/78
H01L 21/308
H01L 21/762

Abstract:

A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.

Nanosheet Single Gate (Sg) And Extra Gate (Eg) Field Effect Transistor (Fet) Co-Integration

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US Patent:

20190378906, Dec 12, 2019

Filed:

Jun 12, 2018

Appl. No.:

16/006173

Inventors:

- Armonk NY, US
Siva Kanakasabapathy - Pleasanton CA, US
Kangguo Cheng - Schenectady NY, US
Jingyun Zhang - Albany NY, US

International Classification:

H01L 29/423
H01L 29/66
H01L 21/311
H01L 21/28

Abstract:

A method of forming a semiconductor device that includes providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness; and forming a oxide layer on the first and second stack of nanosheets. The oxide layer fills a space between said nanosheets in the first stack, and is conformally present on the nanosheets in the second stack. The method further includes forming a work function metal layer on the first and second stack of nanosheets. In some embodiments, the work function metal layer is present on only exterior surfaces of the first stack to provide a single gate structure and is conformally present about an entirety of the nanosheets in the second stack to provide a multiple gate structure.

Gate Cut In Rmg

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US Patent:

20190371912, Dec 5, 2019

Filed:

May 29, 2018

Appl. No.:

15/991128

Inventors:

- Armonk NY, US
Siva Kanakasabapathy - Pleasanton CA, US
Andrew M. Greene - Albany NY, US

International Classification:

H01L 29/66
H01L 21/762
H01L 21/308
H01L 21/306
H01L 21/027
H01L 21/8234
H01L 27/088
H01L 21/768
H01L 29/78

Abstract:

A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.

Multi-Channel Overlay Metrology

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US Patent:

20190316900, Oct 17, 2019

Filed:

Apr 11, 2018

Appl. No.:

15/950271

Inventors:

- Armonk NY, US
Siva Kanakasabapathy - Pleasanton CA, US
Nelson Felix - Slingerlands NY, US

International Classification:

G01B 11/27

Abstract:

An overlay metrology system includes a multi-channel energy unit that selectively operates in a first mode to deliver first photons having a first wavelength to an object under test, and a second mode to deliver second photons to the object under test. The second photons have a second wavelength different from the first wavelength. The overlay metrology system further includes an electronic controller that selectively activates either the first mode or the second mode based at least in part on at least one characteristic of an object under test, and that generates the first protons or the second photons to detect at least one buried structure included in the object under test.

Gate Cut Using Selective Deposition To Prevent Oxide Loss

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US Patent:

20190259665, Aug 22, 2019

Filed:

May 3, 2019

Appl. No.:

16/402343

Inventors:

- Armonk NY, US
Ekmini Anuja De Silva - Slingerlands NY, US
Siva Kanakasabapathy - Pleasanton CA, US

International Classification:

H01L 21/8234
H01L 29/66
H01L 21/28
H01L 29/78
H01L 21/3213
H01L 21/8238

Abstract:

Semiconductor devices include a semiconductor fin. A gate stack is formed over the semiconductor fin. Source and drain regions are formed at respective sides of the gate stack. A dielectric line is formed parallel to the gate stack. An interlayer dielectric is formed between the gate stack and the dielectric line. A top surface of the interlayer dielectric between the gate stack and the dielectric line is not recessed.