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Simon M Sze

from Palo Alto, CA
Age ~89
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Also known as:
Simon Te Sze, Simon Theresa Sze, Simon Therese Sze, Simon H Sze, Simon N Sze
Phone and address:
602 California Ave, Palo Alto, CA 94301
(650) 464-9668
Related to:
Kevin Q Cameron, 36
Connected to:
Ada Sze, 97Andy C Sze, 38Chuen C Sze, 65Ho L Sze, 60Jacky M Sze, 46Jacob Sze, 42Janie Y Sze, 56Li Sze, 96Lucia Sze, 56Man Sze, 68

Simon Sze Phones & Addresses

  • 602 California Ave, Palo Alto, CA 94301 (650) 464-9668 (650) 327-0000
  • East Palo Alto, CA
  • 476 Timberhead Ln, San Mateo, CA 94404
  • Foster City, CA
  • 132 Burlington Rd, New Providence, NJ 07974 (908) 464-9668
  • Santa Clara, CA

Professional Records

License Records

Simon K Sze

License #:
FMC06605 - Expired
Category:
Food Safety
Issued Date:
Jul 1, 1998
Expiration Date:
Jan 31, 2006
Type:
Certified Food Safety Mgr

Publications

Us Patents

Method For Making Semiconductor Crystal Films

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US Patent:
47372338, Apr 12, 1988
Filed:
Sep 2, 1986
Appl. No.:
6/901975
Inventors:
Avid Kamgar - Millington NJ
Ernest Labate - South Plainfield NJ
Joseph R. Ligenza - Flanders NJ
Simon M. Sze - New Providence NJ
Assignee:
American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ
International Classification:
C30B 1322
US Classification:
15662073
Abstract:
Semiconductor crystal films on a dielectric substrate are advantageously made by a zone melting method. Single-crystal structure is initiated at a seed surface, and made to extend across a dielectric surface by melting and resolidifying. Melting is effected upon irradiation with optical radiation which is focused onto an elongated zone; the zone is moved so as to locally melt successive portions of a layer of precursor material which may be amorphous or polycrystalline. The use of incoherent radiation is convenient, and focusing is typically by using a reflector. The process is conveniently effected under a controlled atmosphere and the layer being crystallized may be encapsulated so that no free semiconductor surface is exposed to an atmosphere.

Packaging Microminiature Devices

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US Patent:
H289, Feb 3, 1987
Filed:
Feb 17, 1984
Appl. No.:
6/581336
Inventors:
Kwok K. Ng - Union NJ
Simon M. Sze - Berkeley Heights NJ
Assignee:
AT&T Bell Laboratories - Murray Hill NJ
International Classification:
H01L 2316
H01L 2904
H01L 2100
US Classification:
357 75
Abstract:
One or more silicon-integrated-circuit chips are attached, active side up, to the top side of a silicon wafer. The top side of the wafer and all but peripheral portions of the attached chip(s) are then coated with an etch-resistant layer. Subsequently, the chips are etched to form sloped edges between the active areas of the chips and the top side of the wafer. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped edges to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. In other embodiments, at least one chip of the type described is attached to each side of a wafer. In such embodiments, connections can also be made through vias in the wafer to selectively interconnect pads and/or terminals included on both sides of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

Schottky Barrier Diode Contacts

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US Patent:
39640841, Jun 15, 1976
Filed:
Jun 12, 1974
Appl. No.:
5/478506
Inventors:
John Marshall Andrews - PA NJ
Robert Morgan Ryder - Summit NJ
Simon Min Sze - Murray Hill NJ
Assignee:
Bell Telephone Laboratories, Incorporated - Murray Hill NJ
International Classification:
H01L 2948
H01L 2956
H01L 2964
US Classification:
357 15
Abstract:
A Schottky barrier contact includes a thin layer of high carrier concentration impurities ion implanted over the contact surface of the semiconductor. This reduces the electronic barrier height, increases the tunneling component, and thus reduces the forward-bias turn-on voltage of the diode. The implanted layer has a carrier concentration at least ten times that of the semiconductor substrate, and a thickness smaller than the width of the inherent depletion region resulting from the internally generated electric field at the metal-semiconductor interface. An implanted layer of the opposite conductivity type raises the barrier height.

Semiconductor-On-Insulator (Soi) Devices And Soi Ic Fabrication Method

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US Patent:
47631830, Aug 9, 1988
Filed:
Oct 24, 1986
Appl. No.:
6/921899
Inventors:
Kwok K. Ng - Union NJ
Simon M. Sze - Berkeley Heights NJ
Assignee:
American Telephone and Telegraph Co., AT&T Bell Laboratories - Murray Hill NJ
International Classification:
H01L 2978
H01L 2712
H01L 2980
H01L 2948
US Classification:
357 237
Abstract:
A new SOI device which permits both the kink effect to be avoided and threshold voltage to be regulated, as well as a new method for fabricating SOI ICs, is disclosed. The new device included an electrically conductive pathway extending from the active volume and terminating in a non-active region of the substrate of the device. A back-gate bias is communicated to, and kink-inducing charges are conducted away from, the active volume through the conductive pathway. The new fabrication methd permits SOI ICs to be fabricated using available circuit designs and pattern delineating apparatus, e. g. , IC mask sets. This method involves the formation of a precursor substrate surface which includes islands of insulating material, each of which is encircled by a crystallization seeding area of substantially single crystal semiconductor material. The boundaries of the islands are defined with a first pattern delineating device, e. g. , a mask, which, in terms of the pattern it produces, is substantially identical to a second pattern delineating device.

Method Of Making Contact Electrodes To Silicon Gate, And Source And Drain Regions, Of A Semiconductor Device

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US Patent:
43430821, Aug 10, 1982
Filed:
Apr 17, 1980
Appl. No.:
6/141120
Inventors:
Martin P. Lepselter - Summit NJ
Simon M. Sze - New Providence NJ
Assignee:
Bell Telephone Laboratories, Incorporated - Murray Hill NJ
International Classification:
C23F 102
B01J 1700
B05D 512
C23C 1108
US Classification:
29576B
Abstract:
In the fabrication of a metal oxide semiconductor field effect transistor (MOSFET) or of a metal gate field effect transistor (MESFET), characterized by a polycrystalline silicon gate (13) and a short channel of about a micron or less, a sequence of steps is used involving the simultaneous formation of source, drain, and gate electrode contacts by a bombardment with a transition metal, such as platinum, which forms metal-silicide layers (19, 21, 18) on the source and drain regions (10. 1, 10. 2) as well as the silicon gate electrode (13).

Packaging Microminiature Devices

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US Patent:
46138919, Sep 23, 1986
Filed:
Feb 17, 1984
Appl. No.:
6/581259
Inventors:
Kwok K. Ng - Union NJ
Simon M. Sze - Berkeley Heights NJ
Assignee:
AT&T Bell Laboratories - Murray Hill NJ
International Classification:
H01L 2348
H01L 2944
H01L 2952
US Classification:
357 68
Abstract:
One or more silicon-integrated-circuit chips are attached, active side up, to the bottom side of a silicon wafer. A sloped-wall through-aperture is etched in the wafer in registry with a portion of the active side of each attached chip. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped walls to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

High Speed Lateral Bipolar Transistor

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US Patent:
42596807, Mar 31, 1981
Filed:
Apr 17, 1980
Appl. No.:
6/141119
Inventors:
Martin P. Lepselter - Summit NJ
Simon M. Sze - Murray Hill NJ
Assignee:
Bell Telephone Laboratories, Incorporated - Murray Hill NJ
International Classification:
H01L 2904
H01L 2972
US Classification:
357 35
Abstract:
A bipolar transistor NPN structure (20) is constructed at a major surface of a silicon body with a P-type polycrystalline silicon electrode (13) contacting a P-type base zone (13. 6). Excess acceptor impurities from the polycrystalline silicon electrode (13) are diffused into the base zone (13. 6) in order to tailor its conductivity profile.

Method Of Making Contact Electrodes To Silicon Gate, And Source And Drain Regions, Of A Semiconductor Device

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US Patent:
RE326135, Feb 23, 1988
Filed:
Jul 19, 1985
Appl. No.:
6/756924
Inventors:
Martin P. Lepselter - Summit NJ
Simon M. Sze - Berkeley Heights NJ
Assignee:
American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ
International Classification:
H01L 21265
H01L 2972
C23F 102
US Classification:
437 29
Abstract:
In the fabrication of a metal oxide semiconductor field effect transistor (MOSFET) or of a metal gate field effect transistor (MESFET), characterized by a polycrystalline silicon gate (13) and a short channel of about a micron or less, a sequence of steps is used involving the simultaneous formation of source, drain, and gate electrode contacts by a bombardment with a transition metal, such as platinum, which forms metal-silicide layers (19, 21, 18) on the source and drain regions (10. 1, 10. 2) as well as the silicon gate electrode (13).

Isbn (Books And Publications)

Fundamentals of Semiconductor Fabrication

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Author

Simon M. Sze

ISBN #

0471232793

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Simon M Sze from Palo Alto, CA, age ~89 Get Report