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Shrikant P Lohokare

from San Ramon, CA
Age ~58
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Also known as:
Shirkant Lohokare, Lohokare Shrikant, Shrikant E
Connected to:
Anish S Lohokare, 44Saurabh K Lohokare, 49Alan L Lohr, 66Albert A Lohr, 41Alvie L Lohr, 72Andrew E Lohr, 49Angie A Lohr, 50Bryan J Lohr, 52Cleveland D Lohr, 51Danielle M Lohr, 39

Shrikant Lohokare Phones & Addresses

  • San Ramon, CA
  • 35414 Woodbridge Pl, Fremont, CA 94536 (510) 574-0840
  • 37167 Panton Ter, Fremont, CA 94536 (510) 574-0840
  • Chatsworth, CA
  • Urbana, IL
  • Simi Valley, CA
  • Woodland Hills, CA
  • Alameda, CA
  • Mountain View, CA
  • 35414 Woodbridge Pl, Fremont, CA 94536

Work

Company: Tie launchpad 2013 Position: Mentor

Education

School / High School: Stanford University Graduate School of Business 2004 Specialities: Executive Program

Resumes

Resumes

Shrikant Lohokare Photo 1

Shrikant Lohokare

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Position:
Managing Partner at E-Cubed Ventures, Advisor & Chair at VC TaskForce, Member at TiE
Location:
San Francisco Bay Area
Industry:
Venture Capital & Private Equity
Work:
E-Cubed Ventures since 2009
Managing Partner
VC TaskForce since 2008
Advisor & Chair
TiE since 2008
Member
Skills:
Semiconductors & Electronics
Cleantech & Sustainability
Energy Automation & Control
Nanotechnology & Materials
Venture Capital Investment Mgmt
Deal Making
Due Diligence
Valuation
M&A
Business Planning & Development
Corporate Strategy
Strategic Partnering & Alliances
Leadership & Organization Building
Leading Innovation & Change
Project Management & Execution
IP Strategy & Portfolio Mgmt
Strategic Marketing
Client Relationship Mgmt
Operations Mgmt
Interests:
Innovation Pipeline development Emerging technologies including Semiconductors, Microsystems, Nanotech, Cleantech/ Greentech, Advanced Materials, Energy Automation and Control solutions addressing key market requirements
Honor & Awards:
Co-chair for Front End Process Group at International Technology Roadmap for Semiconductors (ITRS), 2004-2005, 8 US and WW patents granted and multiple pending, Above and Beyond awards for technology and business leadership at Lam Research Corp
Shrikant Lohokare Photo 2

Shrikant Lohokare

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Location:
San Francisco, CA
Industry:
Semiconductors
Shrikant Lohokare Photo 3

Shrikant Lohokare

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Work:
TiE LaunchPad

2013 to 2000
Mentor
eCubed Ventures

2010 to 2000
Founder and Managing Director
eCubed Ventures

2013 to 2014
Managing Director - Corporate & Strategic Marketing
VC Taskforce

2008 to 2013
VC Programs Chair & General Programs Advisory Board Member
VC Taskforce

2011 to 2012
Co-founder & COO
Medical Center of the Americas

2010 to 2012
Managing Consultant - Strategy, Business & Operations Planning
21Ventures

2007 to 2011
Partner & Entrepreneur-in-Residence
21Ventures

2007 to 2010
Board Member
21Ventures

2007 to 2010
Board Member
21Ventures

2007 to 2009
CEO, CTO, and Board Member
Technical Sales & Marketing at KLA-Tencor

2005 to 2007
Director - WW Applications
eCubed Ventures

1998 to 2005
New Business Development
New Products at Plasma & Materials Technologies

1996 to 1998
Technologist/ R&D Manager
University of Illinois at Urbana-Champaign
Urbana-Champaign, IL
1991 to 1996
Research Scientist
Education:
Stanford University Graduate School of Business
2004 to 2005
Executive Program
University of Illinois at Urbana
Urbana-Champaign, IL
1991 to 1996
Ph.D. in Physics
Indian Institute of Technology
Mumbai, Maharashtra
1986 to 1991
Master of Technology in Chemical Engineering

Business Records

Name / Title
Company / Classification
Phones & Addresses
Shrikant Lohokare
Mbr
TECH2BIZ Ventures LLC
Business Consulting Srvcs
2608 Pne Vly Dr, Champaign, IL 61822
Shrikant Lohokare
Managing
eCubed Ventures
Venture Capital & Private Equity · Consulting · Investor Business Services at Non-Commercial Site
201 Spear St SUITE 1100, San Francisco, CA 94105
124 Jamaica St, Tiburon, CA 94920

Publications

Us Patents

System, Method And Apparatus For Improved Global Dual-Damascene Planarization

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US Patent:
6939796, Sep 6, 2005
Filed:
Mar 14, 2003
Appl. No.:
10/390117
Inventors:
Shrikant P. Lohokare - Fremont CA, US
David Hemker - San Jose CA, US
Joel M. Cook - Warrenton VA, US
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
H01L021/4763
US Classification:
438626, 438631, 438633, 438692, 216 67, 216 78
Abstract:
A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.

Methods And Systems For A Stress-Free Cleaning A Surface Of A Substrate

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US Patent:
7129167, Oct 31, 2006
Filed:
Jun 28, 2004
Appl. No.:
10/879598
Inventors:
Shrikant P. Lohokare - Fremont CA, US
Yunsang Kim - San Jose CA, US
Simon McClatchie - Fremont CA, US
Assignee:
LAM Research Corporation - Fremont CA
International Classification:
H01L 21/44
US Classification:
438677, 438692, 438694, 438758, 438E21228, 134 13, 134 2
Abstract:
A method of cleaning a substrate includes receiving a substrate and applying a stress-free cleaning process to the top surface of the substrate. The substrate includes a top surface that is substantially free of device dependent planarity nonuniformities and device independent planarity nonuniformities. The top surface also includes a first material and a device structure formed in the first material, the device structure being formed from a second material. The device structure has a device surface exposed. The device surface has a first surface roughness. A system for stress-free cleaning a substrate is also described.

System, Method And Apparatus For Self-Cleaning Dry Etch

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US Patent:
7140374, Nov 28, 2006
Filed:
Mar 16, 2004
Appl. No.:
10/802460
Inventors:
Shrikant P. Lohokare - Fremont CA, US
Arthur M. Howald - Pleasanton CA, US
Yunsang Kim - San Jose CA, US
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
B08B 9/00
B44C 1/22
US Classification:
134 221, 216 67, 216 74, 216 79, 134 11, 134 12, 134 13, 134 2214, 438905
Abstract:
A method for cleaning a processing chamber that includes heating an inner surface of the processing chamber to a first temperature. The first temperature can be sufficient to cause a first species to become volatile. The first species can be one of several species deposited on the inner surface. A cleaning chemistry is injected into the processing chamber. The cleaning chemistry can be reactive with a second one of the species to convert the second species to the first species. The volatilized first species can also be output from the processing chamber. A system for cleaning the process chamber is also described.

System And Method For Stress Free Conductor Removal

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US Patent:
7217649, May 15, 2007
Filed:
Jan 30, 2004
Appl. No.:
10/769522
Inventors:
Shrikant P. Lohokare - Fremont CA, US
Assignee:
LAM Research Corporation - Fremont CA
International Classification:
H01L 21/4763
US Classification:
438622, 438626, 438631
Abstract:
A system and method for forming a semiconductor in a dual damascene structure including receiving a patterned semiconductor substrate. The semiconductor substrate having a first conductive interconnect material filling multiple features in the pattern. The first conductive interconnect material having an overburden portion. The over burden portion is planarized. The over burden portion is substantially entirely removed in the planarizing process. A mask layer is reduced and a subsequent dielectric layer is formed on the planarized over burden portion. A mask is formed on the subsequent dielectric layer. One or more features are formed in the subsequent dielectric layer and the features are filled with a second conductive interconnect material.

System And Method For Surface Reduction, Passivation, Corrosion Prevention And Activation Of Copper Surface

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US Patent:
7232766, Jun 19, 2007
Filed:
Jan 30, 2004
Appl. No.:
10/769408
Inventors:
Shrikant P. Lohokare - Fremont CA, US
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
H01L 21/302
US Classification:
438714, 438715, 438742
Abstract:
A system and method of passivating an exposed conductive material includes placing a substrate in a process chamber and injecting a hydrogen species into the process chamber. A hydrogen species plasma is formed in the process chamber. A surface layer species is reduced from a top surface of the substrate is reduced. The reduced surface layer species are purged from the process chamber.

Accurate Temperature Measurement For Semiconductor Applications

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US Patent:
7380982, Jun 3, 2008
Filed:
Apr 1, 2005
Appl. No.:
11/097063
Inventors:
Shrikant Lohokare - Fremont CA, US
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
G01K 1/00
G01K 3/06
G01K 3/14
G01K 11/20
G01K 11/06
G01J 5/28
US Classification:
374137, 374160, 374120, 374112, 250337, 25033906
Abstract:
A temperature sensing component enables accurate in situ temperature measurement. The temperature sensing component is disposed within the process chamber. The temperature sensing component has a cavity, in which a transparent cover is disposed over an opening of the cavity. A material is disposed within the cavity of the temperature sensing component, and a sensor is configured to sense a phase change of the material through the transparent cover.

Method For Adjusting Voltage On A Powered Faraday Shield

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US Patent:
7413673, Aug 19, 2008
Filed:
Apr 19, 2005
Appl. No.:
11/109921
Inventors:
Shrikant P. Lohokare - Fremont CA, US
Andras Kuthi - Thousand Oaks CA, US
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
H03J 3/12
US Classification:
216 61, 438714, 438729
Abstract:
An apparatus and method for adjusting the voltage applied to a Faraday shield of an inductively coupled plasma etching apparatus is provided. An appropriate voltage is easily and variably applied to a Faraday shield such that sputtering of a plasma can be controlled to prevent and mitigate deposition of non-volatile reaction products that adversely affect an etching process. The appropriate voltage for a particular etching process or step is applied to the Faraday shield by simply adjusting a tuning capacitor. It is not necessary to mechanically reconfigure the etching apparatus to adjust the Faraday shield voltage.

Methods And Arrangement For The Reduction Of Byproduct Deposition In A Plasma Processing System

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US Patent:
7959984, Jun 14, 2011
Filed:
Dec 22, 2004
Appl. No.:
11/022982
Inventors:
Shrikant P. Lohokare - Fremont CA, US
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
H05H 1/24
US Classification:
427569, 118723 R
Abstract:
In a plasma processing system, a method of reducing byproduct deposits on a set of plasma chamber surfaces of a plasma processing chamber is disclosed. The method includes providing a deposition barrier in the plasma processing chamber, the deposition barrier is configured to be disposed in a plasma generating region of the plasma processing chamber, thereby permitting at least some process byproducts produced when a plasma is struck within the plasma processing chamber to adhere to the deposition barrier and reducing the byproduct deposits on the set of plasma processing chamber surfaces.
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Shrikant P Lohokare from San Ramon, CA, age ~58 Get Report