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Shiyou Zhao

from Boise, ID
Age ~57
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Related to:
Zhao Shiyou, 57Yao Zhao
Connected to:
Alicia E Zhao, 29Allan Zhao, 29Anni Zhao, 37April Zhao, 67Beiping Zhao, 39Betty Y Zhao, 55Bohan Zhao, 32Brandon A Zhao, 32Byron D Zhao, 57Can Zhao, 36

Shiyou Zhao Phones & Addresses

  • 4833 Sagewood Ct, Boise, ID 83716
  • West Lafayette, IN

Work

Position: Protective Service Occupations

Resumes

Resumes

Shiyou Zhao Photo 1

Signal Integrity Engineer

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Location:
Boise, ID
Industry:
Semiconductors
Work:
Micron Technology
Signal Integrity engineer
Education:
Purdue University 1996 - 2001
Ph.D, Electrical and Computer Engineering Fudan University 1990 - 1995
MS, Physics
Skills:
Semiconductors
Signal Integrity
Shiyou Zhao Photo 2

Shiyou Zhao

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Location:
Boise, ID
Industry:
Semiconductors
Work:
Micron Technology
Signal Integrity Engineer
Shiyou Zhao Photo 3

Signal Integrity Engineer At Micron Technology

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Position:
Signal Integrity Engineer at Micron Technology
Location:
Boise, Idaho Area
Industry:
Semiconductors
Work:
Micron Technology
Signal Integrity Engineer

Publications

Us Patents

Method For Forming A Circuit Board Via Structure For High Speed Signaling

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US Patent:
7676919, Mar 16, 2010
Filed:
Sep 19, 2006
Appl. No.:
11/533005
Inventors:
Shiyou Zhao - Boise ID, US
Houfei Chen - Boise ID, US
Hao Wang - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01K 3/10
US Classification:
29852, 29846, 29847, 29849, 29851, 29853, 174250, 174255, 174262, 174266
Abstract:
A method for forming a via in a printed circuit board is disclosed, which via allows for the passage of a signal from one signal plane to another in the (PCB), and in so doing transgresses the power and ground planes between the signal planes. The method comprises forming a first conductive layer on a first side of a circuit board, and forming a second conductive layer on a second side of the circuit board; forming a first hole in the first side of the circuit board; forming a first cylinder on vertical edges of the first hole and in contact with the first conductive layer; forming a second hole in the second side of the circuit board; forming a second cylinder on vertical edges of the first hole, wherein the second cylinder is surrounded by first cylinder and in contact with the second conductive layer; and forming a via in the circuit board, wherein the via is surrounded by the second cylinder.

Substrates, Systems, And Devices Including Structures For Suppressing Power And Ground Plane Noise, And Methods For Suppressing Power And Ground Plane Noise

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US Patent:
7778039, Aug 17, 2010
Filed:
May 8, 2006
Appl. No.:
11/430540
Inventors:
Houfei Chen - Boise ID, US
Shiyou Zhao - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H05K 1/18
US Classification:
361763, 361780, 361761, 361794, 3613011, 3613062, 3613063
Abstract:
Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.

Substrates, Systems, And Devices Including Structures For Suppressing Power And Ground Plane Noise, And Methods For Suppressing Power And Ground Plane Noise

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US Patent:
8508950, Aug 13, 2013
Filed:
Jul 23, 2010
Appl. No.:
12/842637
Inventors:
Houfei Chen - Boise ID, US
Shiyou Zhao - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H05K 1/18
US Classification:
361763, 361761, 361780, 361794, 3613011, 3613062, 3613063, 174262, 174265
Abstract:
Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The at least one noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.

Method For Forming A Circuit Board Via Structure For High Speed Signaling

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US Patent:
8516695, Aug 27, 2013
Filed:
Jul 26, 2011
Appl. No.:
13/190597
Inventors:
Shiyou Zhao - Boise ID, US
Houfei Chen - Boise ID, US
Hao Wang - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01K 3/10
US Classification:
29852, 29846, 29853
Abstract:
One embodiment of the invention comprises an improved method for making a via structure for use in a printed circuit board (PCB). The via allows for the passage of a signal from one signal plane to another in the (PCB), and in so doing transgresses the power and ground planes between the signal plane. To minimize EM disturbance between the power and ground planes, signal loss due to signal return current, and via-to-via coupling, the via is shielded within two concentric cylinders, each coupled to one of the power and ground planes.

Method For Forming A Circuit Board Via Structure For High Speed Signaling

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US Patent:
7992297, Aug 9, 2011
Filed:
Feb 3, 2010
Appl. No.:
12/699428
Inventors:
Shiyou Zhao - Boise ID, US
Houfei Chen - Boise ID, US
Hao Wang - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01K 3/10
US Classification:
29852, 29846, 29847, 29849, 29851, 29853, 174250, 174255, 174262, 174266
Abstract:
One embodiment of the invention comprises an improved method for making a via structure for use in a printed circuit board (PCB). The via allows for the passage of a signal from one signal plane to another in the (PCB), and in so doing transgresses the power and ground planes between the signal plane. To minimize EM disturbance between the power and ground planes, signal loss due to signal return current, and via-to-via coupling, the via is shielded within two concentric cylinders, each coupled to one of the power and ground planes.

Absorbing Boundary For A Multi-Layer Circuit Board Structure

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US Patent:
20060237223, Oct 26, 2006
Filed:
Apr 26, 2005
Appl. No.:
11/114589
Inventors:
Houfei Chen - Boise ID, US
Shiyou Zhao - Boise ID, US
Hao Wang - Boise ID, US
International Classification:
H05K 1/11
US Classification:
174255000, 174262000, 174258000
Abstract:
The invention comprises an improved PCB board design having particular utility for high frequency application, and especially useful to alleviate the problem of electromagnetic disturbance of signals switching through power and ground planes. In one embodiment, the PCB contains a magnetically loaded absorbing boundary to absorb the EM disturbances and keep them from resonating inside the cavity between the power and ground planes. The boundary is preferably placed at an edge or edges of the PCB, where it is unlikely to affect any other signals on the PCB. Exemplary materials for the boundary have a magnetic loss tangent of 1.0 to 1.5 with an attenuation constant of −20 dB/cm over frequencies of interest. Depending on whether the boundary material is solid or non-solid, it may be adhered to the edges of the PCB, or may be applied to the edge and cured. It is preferable that the boundary material span through substantially the entire height of the dielectric cavity between the power and ground planes to best absorb the electromagnetic disturbances.

Circuit Board Via Structure For High Speed Signaling

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US Patent:
20060237227, Oct 26, 2006
Filed:
Apr 26, 2005
Appl. No.:
11/114420
Inventors:
Shiyou Zhao - Boise ID, US
Houfei Chen - Boise ID, US
Hao Wang - Boise ID, US
International Classification:
H05K 1/11
US Classification:
174262000, 174255000
Abstract:
One embodiment of the invention comprises an improved via structure for use in a printed circuit board (PCB), and method for fabricating the same. The via allows for the passage of a signal from one signal plane to another in the (PCB), and in so doing transgresses the power and ground planes between the signal plane. To minimize EM disturbance between the power and ground planes, signal loss due to signal return current, and via-to-via coupling, the via is shielded within two concentric cylinders, each coupled to one of the power and ground planes.

Impedance Matching Via Structure For High-Speed Printed Circuit Boards And Method Of Determining Same

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US Patent:
20070193775, Aug 23, 2007
Filed:
Feb 17, 2006
Appl. No.:
11/357544
Inventors:
Houfei Chen - Boise ID, US
Shiyou Zhao - Boise ID, US
International Classification:
H05K 1/11
H01R 12/04
US Classification:
174262000
Abstract:
An impedance matching conductive via structure that is effectively constructed by selecting an outer conductor and an inner conductor diameter through analytical calculation or numerical simulation, such that impedance of the conductive via structure is matched to the impedance of the conductive signal traces of a printed circuit board. The conductive via structure comprises a conductive barrel that either connects to multiple ground planes or to multiple powers planes and serves as the outer conductor for a coaxial structure that provides a current return path and a matched impedance path of via transition, thus improving the signal transition and reducing signal reflection due to via discontinuity. Moreover, the conductive barrel of the conductive via structure also reduces radiation loss through a parallel plane structure and suppresses coupling between neighboring vias as the energy escaping through the conductive barrel and radiating to other vias is minimized.
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Shiyou Zhao from Boise, ID, age ~57 Get Report